Senior Verification Engineer – Onsite Delft (Analog/Mixed-Signal)

European Tech Recruit; Delft; On-site; EUR 70,000 - 90,000; Full time

Job summary

A leading semiconductor innovator is seeking a Senior Verification Engineer for their Delft office. This fully onsite position focuses on developing SystemVerilog Real-Number Models for analog and mixed-signal circuits, alongside creating verification plans and maintaining UVM environments. Candidates should have over 5 years of verification experience and proficiency in SystemVerilog, Python, and UVM methodologies. Excellent communication skills are essential, and familiarity with Cadence Virtuoso is a plus.

Qualifications

• 5+ (or 8+) years of semiconductor verification experience.
• Strong written and verbal English communication skills.
• Ability to read analog schematics.

Responsibilities

• Develop SystemVerilog Real-Number Models for analog circuits.
• Create verification plans based on specifications.
• Run simulations, analyze results, and debug issues.

Skills

SystemVerilog

UVM-based verification methodologies

Python

Perl

Analog design principles

Verilog

Education

MS (or BS) in Electrical/Computer Engineering

Tools

Cadence Virtuoso

Job description

A leading semiconductor innovator is seeking a Senior Verification Engineer for their Delft office. This fully onsite position focuses on developing SystemVerilog Real-Number Models for analog and mixed-signal circuits, alongside creating verification plans and maintaining UVM environments. Candidates should have over 5 years of verification experience and proficiency in SystemVerilog, Python, and UVM methodologies. Excellent communication skills are essential, and familiarity with Cadence Virtuoso is a plus.