Senior PLL Design Engineer — Mixed-Signal CMOS, On-Site NL

Ethernovia; Utrecht; On-site; EUR 75,000 - 90,000; Full time

Benefits offered by this job

Competitive package including stock options

25 vacation days plus an extra day per year

International work environment

Excellent career and development opportunities

Job summary

Ethernovia is seeking a Senior PLL Design Engineer to join our Mixed-Signal design team in Zeist, Netherlands. You will be involved in the architecture and implementation of advanced Phase-Locked Loops, collaborating closely with various technical teams.

This full-time role requires a Master's or PhD degree in Electrical Engineering and at least 8 years of experience in PLL design. The company offers a competitive package, excellent career development opportunities, and a supportive organizational culture.

Qualifications

• At least 8 years of experience in PLL design in advanced CMOS nodes.
• Team player with experience working in Mixed-Signal IC design teams.
• Excellent communication skills and fluent in English.

Responsibilities

• Drive the architecture and implementation of advanced PLLs.
• Plan and execute a full design cycle from specification to production.
• Collaborate closely with Analog Front-End, DSP, and System teams.

Skills

PLL design

Mixed-Signal IC design

Advanced CMOS processes

RTL

Verilog

C++

Python

Ethernet AFEs

Education

MSc or PhD degree in Electrical Engineering

Job description

Ethernovia is seeking a Senior PLL Design Engineer to join our Mixed-Signal design team in Zeist, Netherlands. You will be involved in the architecture and implementation of advanced Phase-Locked Loops, collaborating closely with various technical teams.

This full-time role requires a Master's or PhD degree in Electrical Engineering and at least 8 years of experience in PLL design. The company offers a competitive package, excellent career development opportunities, and a supportive organizational culture.