Analog IC Design Engineer - PLL Expert

IC Resources; Den Haag; On-site; EUR 90,000 - 140,000; Full time

Job summary

IC Resources is seeking an experienced Analog IC Design Engineer to join the team in the Netherlands. This senior role centers on architecture, design and silicon validation of ultra-low-jitter PLLs and frequency synthesisers for precision timing applications.

You will lead PLL architecture, design high-performance blocks, perform phase noise analysis, mentor engineers, and collaborate across the silicon bring-up cycle. On-site in the Netherlands preferred.

Qualifications

• MSc in Electrical Engineering required; PhD preferred.
• Extensive analog mixed-signal IC design experience with PLLs and frequency synthesisers.
• Experience leading projects or mentoring engineers.

Responsibilities

• Lead architecture and development of high-performance PLLs and fractional-N synthesisers.
• Design ultra-low-jitter PLLs using advanced architectures (sampling, sub-sampling, multi-phase).
• Own PLL performance from concept to silicon validation and release.
• Mentor other analog designers and collaborate with cross-functional teams.

Skills

PLL design

frequency synthesisers

VCO design

phase noise analysis

silicon validation

team leadership

Education

MSc in Electrical Engineering

PhD preferred

Tools

Verilog-A

MATLAB

Job description

I am recruiting for an experienced Analog IC Design Engineer who has extensive PLL design experience to join my client’s team. This is a senior-level role focused on the architecture, design and silicon validation of ultra-low-jitter PLLs and frequency synthesisers.

Responsibilities:

• Lead the architecture and development of high-performance PLL and fractional-N frequency synthesiser solutions for precision timing applications
• Design ultra-low-jitter PLLs using advanced architectures, including sampling PLLs, sub-sampling PLLs and multi-phase PLLs
• Own PLL performance from initial concept through silicon validation and production release
• Design and optimise key PLL blocks including VCOs, DCOs, charge pumps, phase frequency detectors, loop filters, dividers, TDCs and delta sigma modulators
• Perform phase noise, jitter and power analysis to achieve demanding performance targets
• Develop behavioural and system models using tools such as Verilog-A and MATLAB
• Improve supply noise rejection and reduce power supply jitter sensitivity through circuit and architecture optimisation
• Support EM simulations, layout optimisation and floor planning activities
• Work closely with cross-functional teams during silicon bring-up and product development
• Provide technical guidance and mentorship to other analog designers

Requirements:

• MSc in Electrical Engineering required, PhD preferred
• 8+ years of experience in analog mixed signal IC design, with strong expertise in PLLs and frequency synthesisers
• Proven experience designing high-performance fractional-N PLLs with ultra-low jitter performance
• Strong knowledge of PLL architecture, modelling, phase noise, jitter budgeting and circuit optimisation
• Experience with PLL silicon validation and lab characterisation using relevant measurement equipmentUnderstanding of EM simulation and layout optimisation techniques
• Previous experience leading projects or mentoring engineers
• Strong communication skills and ability to work in a collaborative engineering environment

If you have expertise in PLL design and are happy to work full-time on-site in Germany or the Netherlands, please contact Parm Shergill at IC Resources.