Expert PLL Design Engineer

IC Resources; Delft; On-site; EUR 120,000 - 170,000; Full time

Benefits offered by this job

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Health, dental, and vision insurance

Paid time off

Job summary

IC Resources is seeking an Expert PLL Design Engineer to own the architecture, design, and silicon validation of ultra-low-jitter PLLs and frequency synthesizers. The role involves leading PLL development from concept to production in a fast-paced, collaborative environment.

The ideal candidate holds an MS in EE with 8+ years in analog/mixed-signal PLL design, including proof of concept, lab characterization, and team leadership.

Qualifications

• MS in Electrical Engineering; PhD preferred.
• 8+ years in high-performance analog/mixed-signal design focusing on PLLs and synthesizers.
• Proven track record of ultra-low-jitter, power-efficient fractional-N PLLs.
• Hands-on with sampling/sub-sampling/multi-phase PLL architectures.
• Expertise in PLL budgeting for phase-noise, jitter, and power.
• Experience with lab characterization using phase-noise/spectrum analyzers and jitter tools.
• Excellent written and verbal communication skills.
• Proven experience leading/supervising teams.

Responsibilities

• Define and develop ultra-low-jitter PLL and fractional-N frequency synthesizer architectures for precision timing products.
• Architect and design high-performance PLLs
• Design and simulate critical PLL sub-blocks, including VCOs/DCOs, charge pumps, phase-frequency detectors, loop filters, dividers, delta-sigma modulators, and time-to-digital converters (TDCs).
• Perform phase-noise and jitter budgeting across the loop to achieve sub-50 fs integrated jitter.
• Write detailed block-level PLL specifications and behavioral/system models (e.g., Verilog-A, MATLAB).
• Drive electromagnetic (EM) simulations of critical passives and interconnects to optimise layout and floor-planning.
• Collaborate with cross-functional teams to integrate PLL designs, achieve rapid silicon bring-up, and enable fast production release.
• Supervise and mentor junior and senior analog circuit designers.

Skills

PLL design

Analog/mixed-signal design

Phase-noise budgeting

Jitter budgeting

Lab characterization

Education

MS in Electrical Engineering

PhD preferred

Tools

Verilog-A

MATLAB

Phase-noise analyzers

Spectrum analyzers

Jitter measurement tools

Job description

We are seeking a highly skilled and experienced Expert PLL Design Engineer to join our team. This role is pivotal in the architecture, design, and silicon validation of ultra-low-jitter phase-locked loops (PLLs) and frequency synthesizers. The successful candidate will take ownership of PLL performance from concept through production release, ensuring high-quality, spec-compliant designs. If you are passionate about cutting-edge technology and thrive in a collaborative, fast-paced environment, we encourage you to apply. Applications from all over the world are welcome and will be considered depending on suitability. Visa can be provided. The opportunity is office based in The Netherlands or Germany.

Responsibilities

• Define and develop ultra-low-jitter PLL and fractional-N frequency synthesizer architectures for precision timing products.
• Architect and design high-performance PLLs
• Design and simulate critical PLL sub-blocks, including VCOs/DCOs, charge pumps, phase-frequency detectors, loop filters, dividers, delta-sigma modulators, and time-to-digital converters (TDCs).
• Perform phase-noise and jitter budgeting across the loop to achieve sub-50 fs integrated jitter.
• Write detailed block-level PLL specifications and behavioral/system models (e.g., Verilog-A, MATLAB).
• Drive electromagnetic (EM) simulations of critical passives and interconnects to optimise layout and floor-planning.
• Collaborate with cross-functional teams to integrate PLL designs, achieve rapid silicon bring-up, and enable fast production release.
• Supervise and mentor junior and senior analog circuit designers.

Qualifications

• MS in Electrical Engineering required; PhD preferred.
• 8+ years of experience in high-performance analog/mixed-signal circuit design, with a primary focus on PLLs and frequency synthesizers.
• Proven track record of designing ultra-low-jitter, power-efficient fractional-N PLLs achieving.
• Hands‑on experience with advanced PLL architectures such as sampling PLLs, sub‑sampling PLLs, and multi‑phase PLLs.
• Expertise in PLL architecture development, modeling, design, and budgeting for phase‑noise, jitter, and power.
• Experience with lab characterization of PLLs using phase‑noise analyzers, spectrum analyzers, and jitter measurement tools.
• Excellent written and verbal communication skills.
• Proven experience leading/supervising

Compensation package

• Competitive compensation package including shares.
• Comprehensive health, dental, and vision insurance.
• Generous paid time off and holiday schedule.
• Opportunities for professional growth and development.
• Collaborative and innovative work environment.
• Access to state-of-the-art tools and technologies.