Senior PLL Design Engineer

Ethernovia; Utrecht; On-site; EUR 75,000 - 90,000; Full time

Benefits offered by this job

Competitive package including stock options

25 vacation days plus an extra day per year

International work environment

Excellent career and development opportunities

Job summary

Ethernovia is seeking a Senior PLL Design Engineer to join our Mixed-Signal design team in Zeist, Netherlands. You will be involved in the architecture and implementation of advanced Phase-Locked Loops, collaborating closely with various technical teams.

This full-time role requires a Master's or PhD degree in Electrical Engineering and at least 8 years of experience in PLL design. The company offers a competitive package, excellent career development opportunities, and a supportive organizational culture.

Qualifications

• At least 8 years of experience in PLL design in advanced CMOS nodes.
• Team player with experience working in Mixed-Signal IC design teams.
• Excellent communication skills and fluent in English.

Responsibilities

• Drive the architecture and implementation of advanced PLLs.
• Plan and execute a full design cycle from specification to production.
• Collaborate closely with Analog Front-End, DSP, and System teams.

Skills

PLL design

Mixed-Signal IC design

Advanced CMOS processes

RTL

Verilog

C++

Python

Ethernet AFEs

Education

MSc or PhD degree in Electrical Engineering

Job description

Senior PLL Design Engineer

Summary:

• Ethernovia is a global 7+ year-old silicon solutions provider for Automotive Ethernet with a HQ in Silicon Valley.
• We are growing our Mixed-Signal design team, which is based in Zeist, The Netherlands.
• We have a full-time opening for a Senior PLL designer who will work on-site in a team using advanced CMOS processes
  • Driving the architecture and implementation of advanced PLLs (with challenging performance & efficiency specifications).
• The work typically spans the planning & execution of a full design cycle from;
  • Specification, via study & design, test-chips and their evaluation, all the way to qualification and production.
  • All this not only in close collaboration with the Analog Front-End design and Layout teams, but also with the DSP, Digital, Firmware, and System teams, as well as Marketing & FAEs.
• This obviously requires a strong team-player mentality of all involved, so expect professional colleagues with a focus on the end-goal, as well as the needs of team-members to reach it.
• Furthermore, we are a growing and flexible start-up company which stimulates employees to broaden their experience & skills by learning new & exciting design challenges.

Skills & Qualifications

• A MSc or PhD degree in Electrical Engineering (EE)
• At least 8 years of experience in PLL design in advanced CMOS nodes
  • Preferably also experience with RTL, Verilog, C++ & Python
• Experience in the domain of Ethernet AFEs is a plus
• Team player with experience working in Mixed-Signal IC design teams
• Excellent communication skills
• Fluent in English
• Located in: Utrecht, The Netherlands or willing to locate to the Netherlands

What we offer

• A full-time and indefinite contract
• A competitive package (incl. stock option plan)
• 25 vacation days per year and annually one extra day with a maximum of 30 days
• A fast-growing organization with excellent career and development opportunities
• An open organizational culture where inputs from each are valued
• An international environment with international colleagues and development sites on four continents