Senior Mixed-Signal Design Engineer: CMOS/PLL/Oscillators

European Tech Recruit; Delft; On-site; EUR 80,000 - 110,000; Full time

Job summary

[Unknown] is seeking an experienced Mixed-Signal Design Engineer to contribute to precision timing circuits using the company’s MEMS/Analog technology. The role involves designing analog/mixed-signal blocks, performing simulations and coordinating with layout and characterization teams to ensure silicon success.

The candidate should have a strong CMOS background, expertise in PLLs or MEMS-related areas, and proficiency with MATLAB and Cadence tools. Visas supported and location in Delft, NL.

Qualifications

• MS in Electrical Engineering or PhD in Electrical Engineering with related experience.
• Strong publications with prototypes proven in silicon.
• Detailed knowledge of CMOS circuits and noise analysis.
• Expertise in one of: Integer-N PLL, temperature sensor, analog/digital filters, MEMS oscillator, sub-threshold circuits, low-noise regulator and bandgap, high-speed output drivers.

Responsibilities

• Design analog and mixed-signal circuits meeting specifications.
• Contribute to architectural definition and chip integration.
• Perform design and verification simulations to ensure blocks meet specs at schematic and post-layout extraction stages.
• Oversee layout for critical blocks and validate with layout engineers.
• Document blocks and participate in design reviews; assist in chip bring-up and characterization.
• Collaborate with Product, Characterization, Test and Application Engineers on owned blocks.

Skills

MATLAB

VerilogA

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence analog design tools

Job description

[Unknown] is seeking an experienced Mixed-Signal Design Engineer to contribute to precision timing circuits using the company’s MEMS/Analog technology. The role involves designing analog/mixed-signal blocks, performing simulations and coordinating with layout and characterization teams to ensure silicon success.

The candidate should have a strong CMOS background, expertise in PLLs or MEMS-related areas, and proficiency with MATLAB and Cadence tools. Visas supported and location in Delft, NL.