Senior ADC Design Engineer

Ethernovia; Utrecht; On-site; EUR 75,000 - 95,000; Full time

Benefits offered by this job

25 vacation days plus one additional day per year

Stock option plan

Career development opportunities

Open organizational culture

Job summary

Ethernovia in Utrecht is seeking a Senior ADC Design Engineer to lead the architecture and implementation of advanced ADCs. You will collaborate with diverse teams and execute the full design cycle from specification through to production.

The ideal candidate holds an MSc or PhD in Electrical Engineering and has at least 8 years of experience in ADC design. Benefits include a competitive package with stock options and excellent career opportunities.

Qualifications

• At least 8 years of experience in ADC design in advanced CMOS nodes.
• Experience in the Ethernet AFE domain is a plus.
• Fluent in English.

Responsibilities

• Engineers the architecture and implementation of advanced ADCs.
• Planned and executed the full design cycle from study to production.
• Collaborated with various teams to meet design goals.

Skills

ADC design

Mixed-Signal IC design

Verilog

C++

Python

Communication skills

Team player

Education

MSc or PhD in Electrical Engineering

Job description

Senior ADC Design Engineer

Responsibilities

• Engineers the architecture and implementation of advanced ADCs with challenging performance and efficiency specifications.
• Planned and executed the full design cycle from specification and study to design, test chips, evaluation, qualification and production.
• Collaborated with Analog Front-End, Layout, DSP, Digital, Firmware, System, Marketing, and FAEs teams to meet design goals.
• Worked on‑site in a team using advanced CMOS processes in Zeist, The Netherlands.
• Strong team‑player mentality, supporting team members to achieve objectives.
• Engaged with a flexible, startup environment to broaden experience and skills on new design challenges.

Skills & Qualifications

• MSc or PhD in Electrical Engineering.
• At least 8 years of experience in ADC design in advanced CMOS nodes.
• Experience with RTL, Verilog, C++, and Python.
• Experience in Ethernet AFE domain is a plus.
• Team player with experience in Mixed‑Signal IC design teams.
• Excellent communication skills.
• Fluent in English.
• Located in or willing to relocate to Utrecht, The Netherlands.

What We Offer

• Full‑time and indefinite contract.
• Competitive package including stock option plan.
• 25 vacation days, plus one additional day per year, with a maximum of 30 days.
• Fast‑growing organization with excellent career and development opportunities.
• Open organizational culture where inputs from each colleague are valued.
• International environment with colleagues and development sites on four continents.