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NXP Semiconductors NV in Nijmegen seeks an experienced Senior Package Design Engineer to lead advanced semiconductor package design for RF, mmWave, and mixed-signal applications across NR and Automotive lines. You will drive die-package-PCB codesign, optimize layouts, and ensure manufacturability and reliability from concept to release.
The role requires 5+ years in flip-chip/WLCSP packaging, proficiency in APD and AutoCAD, and strong PISI knowledge.
The Package Innovation (PI) department is an organization within NXP's Corporate Technology Office that develops advanced semiconductor packaging solutions and next-generation packaging technologies across all NXP product lines. The Package Design team is a centralized global function responsible for package development and package design execution across NXP. This position primarily supports the Networking & Radar (NR) and Automotive Processing & Systems business lines developing advanced driver assistance, radar, Vehicle-to-Everything (V2X), wireless high-frequency connectivity, and infotainment solutions for a full spectrum of radio and amplifiers.
Responsible for all aspects of advanced semiconductor package design for mixed signal, RF, microwave, and mmWave products, including package architecture development, die-package codesign, package layout, design rule compliance, manufacturability and reliability optimization, and technical documentation.
Bachelor's or Master's degree in Electrical, Mechanical, Materials Engineering, or equivalent.
Technical experience in the following areas:
Five plus years direct experience designing flip chip and wire-bond substrate-based and WLCSP/FOWLP semiconductor packages.
Expert proficiency with Cadence Allegro Package Designer (APD) and AutoCAD required.
Experience with die-package-PCB codesign methodologies desired.
Knowledge of Power Integrity and Signal Integrity (PISI) and high-speed signal routing, differential pair implementation, return-path management, and impedance-controlled interconnect design a plus.
Strong understanding of substrate technologies including design rules as well as Geometric Dimensioning and Tolerancing.
Experience with or extensive exposure to primarily analog SoC design prefrred.
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