Analog/Mixed-Signal Design Engineer — Precision Timing

Qabird; Rijswijk; On-site; EUR 90,000 - 120,000; Full time

Job summary

SiTime Corporation is a leading precision timing company focused on MEMS programmable solutions. The Analog Mixed-Signal Circuit Design Engineer will develop precision timing circuits, leveraging MEMS tech for high performance with low power and compact size.

The role spans design, verification, layout coordination and cross‑functional collaboration. Candidates will contribute to architectural definitions, device integration and chip bring‑up, with emphasis on owned blocks and thorough

Qualifications

• M.S. or Ph.D. in Electrical Engineering
• Strong academic record with published research prototyped and proven in silicon
• Detailed knowledge of CMOS circuits and noise analysis
• Experience with analog blocks: PLLs, sensors, ADCs, filters, amplifiers, regulators
• Programming in MATLAB and VerilogA
• Proficient with Cadence analog design tools
• Ability to oversee circuit layout for critical blocks

Responsibilities

• Design analog and mixed‑signal circuits meeting architectural requirements and specs
• Contribute to architectural definition and chip integration
• Run calculations, design and verification simulations to ensure blocks meet specs
• Work closely with Layout Engineers to validate proper layout
• Document blocks and lead design review meetings
• Participate in chip bring‑up, evaluation and characterization
• Collaborate with Product, Characterization, Test and Application Engineers
• Support other projects as needed by management or business needs

Skills

MATLAB

VerilogA

Education

M.S. or Ph.D. in Electrical Engineering

Tools

Cadence analog design tools

Job description

SiTime Corporation is a leading precision timing company focused on MEMS programmable solutions. The Analog Mixed-Signal Circuit Design Engineer will develop precision timing circuits, leveraging MEMS tech for high performance with low power and compact size.

The role spans design, verification, layout coordination and cross‑functional collaboration. Candidates will contribute to architectural definitions, device integration and chip bring‑up, with emphasis on owned blocks and thorough