Senior FPGA DSP IP Architect

Lattice Semiconductor; Penang; On-site; MYR 180,000 - 320,000; Full time

Job summary

Lattice Semiconductor in Penang, Malaysia, seeks an experienced FPGA/IP engineer to design and develop DSP foundation IP and IP catalog tooling. You will collaborate with cross-functional teams to plan releases, analyze requirements, scope features, and drive quality through testing and validation.

The role requires strong RTL skills (Verilog/VHDL/SystemVerilog), DSP theory knowledge, and a track record in IP design or ASIC/FPGA engineering. Malaysian right-to-work is required.

Qualifications

• Bachelor’s or Master’s degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline.
• 8+ years of experience in IP design or ASIC/FPGA engineering.
• Strong proficiency in RTL design using Verilog, VHDL, or SystemVerilog.
• Working experience in DSP theory and algorithms: filtering, FFT, fixed-point arithmetic, sample-rate conversion.

Responsibilities

• Design and implement DSP-centric foundation IP blocks for FPGA fabric.
• Develop RTL (Verilog/VHDL/SystemVerilog) for DSP hard macros and programmable DSP slices.
• Perform functional simulation and timing analysis to ensure correctness and performance targets.
• Engage with software and tools teams to ensure DSP IP is correctly modeled in simulation libraries and synthesis flows.

Skills

RTL design

Verilog

VHDL

SystemVerilog

DSP theory

IP design

FPGA engineering

Education

Bachelor's or Master's in Electronics/Electrical Engineering or Computer Engineering

Tools

Synopsys Design Compiler

PrimeTime

Radiant

Quartus

Job description

Lattice Semiconductor in Penang, Malaysia, seeks an experienced FPGA/IP engineer to design and develop DSP foundation IP and IP catalog tooling. You will collaborate with cross-functional teams to plan releases, analyze requirements, scope features, and drive quality through testing and validation.

The role requires strong RTL skills (Verilog/VHDL/SystemVerilog), DSP theory knowledge, and a track record in IP design or ASIC/FPGA engineering. Malaysian right-to-work is required.