SoC Physical Design Engineer – Floorplanning & Signoff

Avecas

Bayan Lepas

On-site

MYR 150,000 - 210,000

Full time

6 days ago
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Job summary

Avecas is seeking a Senior Physical Design Engineer in Bayan Lepas to drive block- and top-level physical design activities, including floorplanning, placement, CTS, routing, and timing closure for complex SoCs. You will collaborate with RTL, DFT, and verification teams to ensure clean handoff and signoff-quality results across PPA metrics.

Daily tasks include static timing, power/IR drop, EM checks, and physical verification while debugging congestion and timing issues.

Qualifications

  • Experience leading physical design for complex SoCs.
  • Strong background in floorplanning, CTS, routing and timing closure.
  • Proficiency with DRC/LVS, antenna checks, and reliability signoff at advanced nodes.
  • Familiarity with RTL design interfaces for ECOs and handoffs.
  • Hands-on use of Cadence, Synopsys, and Siemens toolchains.

Responsibilities

  • Drive block- and top-level physical design activities from floorplanning to timing closure.
  • Collaborate with RTL, logic, DFT, and verification teams to ensure clean handoff and signoff-quality results.
  • Prepare implementation and signoff reports; contribute to flow improvements.
  • Mentor junior engineers to ensure delivery aligned with schedules.

Skills

Physical Design
Floorplanning
Placement
CTS
Routing
Timing Closure
Power & IR drop
LVS/DRC
RTL Interface

Education

Bachelor’s or Master’s in Electrical/Electronics Engineering or related field

Tools

Cadence
Synopsys
Siemens

Job description

Avecas is seeking a Senior Physical Design Engineer in Bayan Lepas to drive block- and top-level physical design activities, including floorplanning, placement, CTS, routing, and timing closure for complex SoCs. You will collaborate with RTL, DFT, and verification teams to ensure clean handoff and signoff-quality results across PPA metrics.

Daily tasks include static timing, power/IR drop, EM checks, and physical verification while debugging congestion and timing issues.

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