SOC Front End Integration Engineer

UST; Penang; On-site; MYR 90,000 - 120,000; Full time

Job summary

UST in Penang seeks a Front End Integration Engineer to perform IP-level FE Integration tasks. You will focus on synthesis, linting, CDC/LEC, UPF, and related front-end verification.

Exposure to PD and STA flows is highly desirable, with collaboration across verification, architecture, and backend teams to ensure seamless IP integration and handoff.

Qualifications

• Bachelor's degree in Electrical & Electronic Engineering, Computer Engineering, or related field.
• At least 3 years of FEInt experience.
• Proficiency in RTL design and SystemVerilog.
• Experience with Perl, Python, or TCL scripting.
• Experience with EDA tools and verification (VCS/Verdi/DVE) is a plus.

Responsibilities

• Conduct synthesis and optimization of IP blocks.
• Perform linting to ensure code quality and adherence to design guidelines.
• Conduct CDC analysis to identify and address clock domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis.
• Implement UPF methodologies for power-aware design and low-power verification.
• Collaborate with verification, architecture, and backend teams for IP integration.

Skills

Synthesis

Linting

CDC

LEC

UPF

RTL design

SystemVerilog

Perl

Python

TCL

EDA tools

AMBA/AXI/AHB protocols

Education

Bachelor's degree in Electrical & Electronic Engineering, Computer Engineering, or related field

Tools

VCS

Verdi

DVE

Job description

We are seeking a Front End Integration Engineer to perform IP-level FE Integration (FEInt) tasks. The ideal candidate will have expertise in synthesis, linting, CDC (Clock Domain Crossing), LEC (Logical Equivalence Checking), UPF (Unified Power Format), and related front-end implementation and verification methodologies. Exposure to Physical Design (PD) and Static Timing Analysis (STA) flows is highly desirable.

Responsibilities:

• Conduct synthesis and optimization of IP blocks.
• Perform linting to ensure code quality and adherence to design guidelines.
• Conduct CDC analysis to identify and address potential clock domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis.
• Implement UPF methodologies for power-aware design and low-power verification.
• Collaborate with verification, architecture, and backend teams to ensure seamless IP integration and handoff.

Qualifications:

• Bachelor's degree in Electrical & Electronic Engineering, Computer Engineering, or a related field.
• At least 3 years of experience in Front End Integration (FEInt) tasks.
• Strong expertise in synthesis, linting, CDC, LEC, and UPF methodologies.
• Good understanding of RTL design and SystemVerilog. Proficiency in scripting languages such as Perl, Python, or TCL.
• Proficient in industry-standard EDA tools.
• Rich verification experience (block-level or SoC-level); simulation and formal verification experience are additional advantages.
• Strong debugging capabilities with hands-on experience in VCS, Verdi, and DVE tools.
• Familiarity with standard AMBA/AXI/AHB interface protocols.
• Strong problem-solving, analytical, communication, and teamwork skills.