ASIC Front End Integration Engineer (FEINT)

UST Global; Bayan Lepas; On-site; MYR 90,000 - 140,000; Full time

Job summary

Jora Malaysia is seeking an ASIC Front End Integration Engineer to perform IP-level FE Integration tasks. The ideal candidate will have expertise in synthesis, linting, CDC (Clock Domain Crossing), LEC (Logical Equivalence Checking), UPF (Unified Power Format), and related front-end implementation and verification methodologies.

Exposure to Physical Design (PD) and Static Timing Analysis (STA) flows is highly desirable.

Qualifications

• Bachelor's degree in Electrical & Electronic Engineering, Computer Engineering, or a related field.
• At least 3 years of experience in Front End Integration (FEInt) tasks.
• Strong expertise in synthesis, linting, CDC, LEC, and UPF methodologies.
• Good understanding of RTL design and SystemVerilog.

Responsibilities

• Conduct synthesis and optimization of IP blocks.
• Perform linting to ensure code quality and adherence to design guidelines.
• Conduct CDC analysis to identify and address potential clock-domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis.
• Implement UPF methodologies for power-aware design and low-power verification.
• Collaborate with verification, architecture, and backend teams to ensure seamless IP integration and handoff.

Skills

Synthesis

Linting

CDC

LEC

UPF

RTL design

SystemVerilog

Perl

Python

TCL

AMBA/AXI/AHB interfaces

Education

Bachelor's degree in Electrical & Electronic Engineering or Computer Engineering

Tools

VCS

Verdi

DVE

Job description

Jora Malaysia will close on 9th September 2026. Thank you for being with us, we are cheering you on as you continue your career journey.

ASIC Front End Integration Engineer (FEINT)

We are seeking a ASIC Front End Integration Engineer to perform IP-level FE Integration (FEInt) tasks. The ideal candidate will have expertise in synthesis, linting, CDC (Clock Domain Crossing), LEC (Logical Equivalence Checking), UPF (Unified Power Format), and related front-end implementation and verification methodologies. Exposure to Physical Design (PD) and Static Timing Analysis (STA) flows is highly desirable.

Responsibilities:

Conduct synthesis and optimization of IP blocks.

Perform linting to ensure code quality and adherence to design guidelines.

Conduct CDC analysis to identify and address potential clock domain crossing issues.

Perform LEC to ensure design consistency before and after synthesis.

Implement UPF methodologies for power-aware design and low-power verification.

Collaborate with verification, architecture, and backend teams to ensure seamless IP integration and handoff.

Qualifications:

Bachelor's degree in Electrical & Electronic Engineering, Computer Engineering, or a related field.

At least 3 years of experience in Front End Integration (FEInt) tasks.

Strong expertise in synthesis, linting, CDC, LEC, and UPF methodologies.

Good understanding of RTL design and SystemVerilog. Proficiency in scripting languages such as Perl, Python, or TCL.

Proficient in industry-standard EDA tools.

Rich verification experience (block-level or SoC-level); simulation and formal verification experience are additional advantages.

Strong debugging capabilities with hands-on experience in VCS, Verdi, and DVE tools.

Familiarity with standard AMBA/AXI/AHB interface protocols.

Strong problem-solving, analytical, communication, and teamwork skills.

Preferred Qualifications:

Knowledge of Physical Design (PD) flows, including floorplanning, place-and-route, power planning, and timing closure concepts.

Experience with Static Timing Analysis (STA) and timing sign-off methodologies.

Familiarity with front-end and back-end design handoff processes.

Understanding of timing constraints development and timing/debug analysis.

Experience working with advanced-node ASIC/SoC development flows is an advantage.