Principal Soft IP Engineer

Oppstar Berhad; Penang; On-site; MYR 300,000 - 450,000; Full time

Job summary

Oppstar Berhad in Penang seeks a Principal Engineer for Soft IP to lead the design and delivery of high-performance digital IP cores. You will bridge architecture with silicon, guiding RTL development and verification across multiple foundry nodes.

This role requires 10+ years in ASIC/SoC design, mastery of Verilog/SystemVerilog, and strong leadership to mentor teams while collaborating with physical design and client engineering during integration and post-silicon validation.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field.
• 10+ years of ASIC/SoC design with focus on IP development (Soft IP/Digital).
• Expertise in Verilog/SystemVerilog and bus protocols (AMBA, PCIe, DDR/LPDDR, CXL).

Responsibilities

• Lead end-to-end design of complex Soft IP cores using Verilog/SystemVerilog.
• Mentor junior and senior design engineers and provide technical direction.
• Define verification strategy with UVM/SystemVerilog and formal methods.
• Collaborate with physical design for timing closure and layout constraints.
• Support clients with integration, debugging, and post-silicon validation.
• Drive adoption of advanced EDA tools and automated flows.

Skills

Verilog/SystemVerilog

IP development

RTL design

CDC

PPA optimization

AMBA AXI/AHB/APB

PCIe/DDR/LPDDR/CXL

Leadership

EDA tools

UVM/SystemVerilog

Education

Bachelor’s or Master’s in Electrical/Electronic Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Job description

As a Principal Engineer for Soft IP, you will play a critical leadership role in the development of high-performance, reusable semiconductor Intellectual Property (IP) cores. You will bridge the gap between architectural theory and final silicon implementation. Your primary responsibility is to lead the design, verification, and delivery of synthesizable RTL (Register Transfer Level) that serves as the building block for our clients' complex SoC (System-on-Chip) designs.

Key Responsibilities

• IP Architecture & Design: Lead the end-to-end design of complex digital Soft IP cores using Verilog/SystemVerilog. Ensure designs are modular, configurable, and optimized for multiple foundry nodes and process technologies.
• Technical Leadership: Mentor junior and senior design engineers. Provide technical direction on RTL coding standards, power/performance/area (PPA) optimization, and design-for-reuse strategies.
• Verification Strategy: Collaborate with verification teams to ensure 100% functional coverage. Define and oversee the development of testbenches (UVM/SystemVerilog) and formal verification methodologies to ensure "first-time-right" silicon.
• Cross-Functional Integration: Work closely with physical design teams to provide necessary constraints (SDC) and guidance for synthesis, timing closure, and layout integration.
• Customer Support: Act as the primary technical point of contact for clients integrating our IP, providing support for integration, debugging, and post-silicon validation.
• Methodology Innovation: Drive the adoption of advanced EDA tools and automated design flows to improve design cycle efficiency and product quality.

Required Qualifications

• Education: Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or related fields.
• Experience: 10+ years of experience in ASIC/SoC design, with a strong focus on IP development (Soft IP/Digital Design).
• Technical Expertise:

-Expertise in Verilog / SystemVerilog and hardware description languages.

-In-depth knowledge of standard bus protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR/LPDDR, CXL).

-Strong understanding of digital design fundamentals, clock domain crossing (CDC), and power-aware design (UPF/CPF).

• Tools: Proficient with industry-standard EDA tools (Synopsys, Cadence, or Mentor Graphics) for simulation, synthesis, and static timing analysis.
• Soft Skills: Proven ability to lead technical teams, manage client expectations, and communicate complex technical concepts clearly