ASIC Front-End Integration Engineer: IP, CDC & UPF

UST Global; Bayan Lepas; On-site; MYR 100,000 - 167,000; Full time

Job summary

Jora Malaysia is seeking an ASIC Front-End Integration Engineer (RTL, Synthesis, CDC, LEC, UPF) to join our IP-level FE Integration team. The role focuses on IP synthesis, linting, CDC/LEC, UPF methods, and collaboration with verification and backend teams.

Exposure to Physical Design (PD) and STA flows is highly desirable. A bachelor's degree in Electrical/Computer Engineering and at least 3 years FEInt experience are required, with strong skills in SystemVerilog and EDA tools.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum 3 years of FEInt experience.
• Strong expertise in synthesis, linting, CDC, LEC, and UPF.
• Proficiency in RTL design and SystemVerilog.
• Experience with VCS/Verdi/DVE tools.

Responsibilities

• Conduct synthesis and optimization of IP blocks.
• Perform linting to ensure code quality and adherence to design guidelines.
• Conduct CDC analysis to identify clock domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis.
• Implement UPF methodologies for power-aware design and verification.
• Collaborate with verification, architecture, and backend teams for IP integration and handoff.

Skills

Front End Integration

Synthesis

Linting

CDC

LEC

UPF

SystemVerilog

Perl

Python

TCL

VCS

Verdi

DVE

RTL Design

Debugging

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

EDA tools

Job description

Jora Malaysia is seeking an ASIC Front-End Integration Engineer (RTL, Synthesis, CDC, LEC, UPF) to join our IP-level FE Integration team. The role focuses on IP synthesis, linting, CDC/LEC, UPF methods, and collaboration with verification and backend teams.

Exposure to Physical Design (PD) and STA flows is highly desirable. A bachelor's degree in Electrical/Computer Engineering and at least 3 years FEInt experience are required, with strong skills in SystemVerilog and EDA tools.