Senior ASIC Front-End Integration Engineer

UST Global; Bayan Lepas; On-site; MYR 90,000 - 140,000; Full time

Job summary

Jora Malaysia is seeking an ASIC Front End Integration Engineer to perform IP-level FE Integration tasks. The ideal candidate will have expertise in synthesis, linting, CDC (Clock Domain Crossing), LEC (Logical Equivalence Checking), UPF (Unified Power Format), and related front-end implementation and verification methodologies.

Exposure to Physical Design (PD) and Static Timing Analysis (STA) flows is highly desirable.

Qualifications

• Bachelor's degree in Electrical & Electronic Engineering, Computer Engineering, or a related field.
• At least 3 years of experience in Front End Integration (FEInt) tasks.
• Strong expertise in synthesis, linting, CDC, LEC, and UPF methodologies.
• Good understanding of RTL design and SystemVerilog.

Responsibilities

• Conduct synthesis and optimization of IP blocks.
• Perform linting to ensure code quality and adherence to design guidelines.
• Conduct CDC analysis to identify and address potential clock-domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis.
• Implement UPF methodologies for power-aware design and low-power verification.
• Collaborate with verification, architecture, and backend teams to ensure seamless IP integration and handoff.

Skills

Synthesis

Linting

CDC

LEC

UPF

RTL design

SystemVerilog

Perl

Python

TCL

AMBA/AXI/AHB interfaces

Education

Bachelor's degree in Electrical & Electronic Engineering or Computer Engineering

Tools

VCS

Verdi

DVE

Job description

Jora Malaysia is seeking an ASIC Front End Integration Engineer to perform IP-level FE Integration tasks. The ideal candidate will have expertise in synthesis, linting, CDC (Clock Domain Crossing), LEC (Logical Equivalence Checking), UPF (Unified Power Format), and related front-end implementation and verification methodologies.

Exposure to Physical Design (PD) and Static Timing Analysis (STA) flows is highly desirable.