Senior STA Engineer – SoC Timing & Closure

AndGate Informatics Pvt. Ltd.; George Town; On-site; MYR 120,000 - 170,000; Full time

Job summary

AndGate Informatics Pvt. Ltd. in Penang, Malaysia is seeking a Static Timing Analysis (STA) Engineer with 3+ years of hands-on experience to drive timing closure for complex SoCs.

You will develop timing constraints, validate them, and debug setup/hold violations, while implementing timing ECOs and optimizing designs. The role requires strong collaboration with RTL, PD, CTS, and Signoff teams to ensure successful tape-out across PVT corners.

Qualifications

• 3+ years of experience with STA for complex SoC designs.
• Strong knowledge of timing constraints development, validation, and debugging.
• Experience with timing closure and ECO implementation.
• Hands-on experience with PrimeTime or equivalent STA tools.
• Good understanding of SDC, STA, CTS, and PVT corners.
• Experience with MCMM analysis and timing ECOs.

Responsibilities

• Perform Static Timing Analysis (STA) for complex SoC designs
• Timing constraints development, validation, and debugging
• Analyze setup/hold violations and perform timing closure
• Timing ECO implementation and optimization
• Collaborate with RTL, PD, CTS, and Signoff teams
• Perform MCMM timing analysis and signoff
• Debug timing issues across different PVT corners
• Generate and analyze timing reports
• Strong knowledge of STA concepts and timing closure
• Hands-on experience with PrimeTime or equivalent STA tools
• Good understanding of SDC, STA, CTS, and PVT corners
• Experience with MCMM analysis and timing ECOs
• Good understanding of ASIC physical design flow
• Strong debugging and problem-solving skills

Skills

STA concepts

Timing closure

Debugging timing issues

MCMM timing analysis

SDC, PVT corners

Collaboration with RTL/PD/CTS/Signoff

Tools

PrimeTime

Job description

AndGate Informatics Pvt. Ltd. in Penang, Malaysia is seeking a Static Timing Analysis (STA) Engineer with 3+ years of hands-on experience to drive timing closure for complex SoCs.

You will develop timing constraints, validate them, and debug setup/hold violations, while implementing timing ECOs and optimizing designs. The role requires strong collaboration with RTL, PD, CTS, and Signoff teams to ensure successful tape-out across PVT corners.