Senior ASIC Synthesis & Timing Engineer

Vhunt4u; Malaysia; On-site; MYR 60,000 - 110,000; Full time

Job summary

Vhunt4u in Malaysia is seeking an ASIC STA/SYNTHESIS engineer to drive timing analysis and RTL synthesis for digital designs. You will optimize performance, power and area, fix setup/hold violations, develop and validate SDC constraints, and collaborate with RTL, DFT and Physical Design teams.

Solid knowledge of Genus and Tempus with industry EDA tools is required, plus experience delivering timing closure through implementation and signoff.

Qualifications

• Bachelor's or Master's in engineering (EEE/EC) with ASIC STA/SYNTHESIS expertise.
• Experience in timing analysis and logic synthesis of digital designs.
• Proven ability to achieve timing closure and optimize performance, power and area.
• Perform RTL synthesis with industry-standard tools.
• Analyze LEC to ensure gate-level netlist matches the original RTL.
• Run STA and identify timing violations; fix setup/hold across corners.
• Develop and validate constraints (SDC).
• Analyze timing reports and improve design quality.
• Collaborate with RTL, DFT and Physical Design teams.
• Support timing closure during implementation and signoff.
• Strong understanding of digital design fundamentals; timing concepts.

Responsibilities

• Drive timing analysis and RTL/logic synthesis for digital designs.
• Fix setup/hold violations across corners and modes.
• Develop and validate SDC constraints.
• Analyze timing reports and optimize design quality.
• Collaborate with RTL, DFT and Physical Design teams to ensure timing closure.
• Support timing closure during implementation and signoff.

Skills

Timing analysis

Logic synthesis

RTL synthesis

Static timing analysis

SDC constraints

Timing closure

EDA tools

Genus

Tempus

Digital design fundamentals

Education

Bachelor's/Master's in Engineering (EEE/EC)

Tools

Genus

Tempus

RTL synthesis tools

Job description

Vhunt4u in Malaysia is seeking an ASIC STA/SYNTHESIS engineer to drive timing analysis and RTL synthesis for digital designs. You will optimize performance, power and area, fix setup/hold violations, develop and validate SDC constraints, and collaborate with RTL, DFT and Physical Design teams.

Solid knowledge of Genus and Tempus with industry EDA tools is required, plus experience delivering timing closure through implementation and signoff.