Senior Soft IP Architect & RTL Lead

Oppstar Berhad; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Oppstar Berhad in Penang seeks a Principal Engineer for Soft IP to lead design, verification, and delivery of synthesizable RTL building blocks for client SoC projects.

You will mentor teams, drive EDA tool adoption, and collaborate with verification and physical design to ensure first-time-right silicon and robust IP across foundry nodes.

This role requires deep HDL expertise and strong communication with customers.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or related fields.
• 10+ years of experience in ASIC/SoC design with a focus on IP development (Soft IP/Digital Design).
• Expertise in Verilog / SystemVerilog and hardware description languages.
• Strong knowledge of standard bus protocols (AMBA AXI/AHB/APB, PCIe, DDR/LPDDR, CXL).

Responsibilities

• Lead end-to-end design of complex Soft IP cores using Verilog/SystemVerilog.
• Mentor junior and senior design engineers; provide direction on RTL coding standards and PPA optimization.
• Collaborate with verification teams to ensure 100% functional coverage and first-time-right silicon.
• Provide constraints (SDC) and guidance for synthesis, timing closure, and layout integration.
• Act as primary technical contact for clients integrating our IP.
• Drive adoption of advanced EDA tools and automated design flows.

Skills

Verilog / SystemVerilog

IP development

CDC

PPA optimization

AMBA AXI/AHB/APB

Digital design fundamentals

Education

Bachelor’s or Master’s in Electrical/Electronic Engineering or Computer Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Job description

Oppstar Berhad in Penang seeks a Principal Engineer for Soft IP to lead design, verification, and delivery of synthesizable RTL building blocks for client SoC projects.

You will mentor teams, drive EDA tool adoption, and collaborate with verification and physical design to ensure first-time-right silicon and robust IP across foundry nodes.

This role requires deep HDL expertise and strong communication with customers.