Lead Soft IP Engineer: RTL/SoC Architect & Mentor

Oppstar Technology; Penang; On-site; MYR 180,000 - 240,000; Full time

Job summary

Oppstar Technology is seeking a Principal Engineer for Soft IP to lead design, verification, and delivery of synthesizable RTL cores for complex SoCs. You will bridge architectural concepts and silicon realization, mentoring engineers and coordinating with verification and physical design teams.

The ideal candidate has 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog skills, and deep knowledge of standard bus protocols (AXI, PCIe, DDR).

Qualifications

• 10+ years of experience in ASIC/SoC design with focus on IP development (Soft IP/Digital Design).
• Expertise in Verilog / SystemVerilog and hardware description languages.
• In-depth knowledge of standard bus protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR/LPDDR, CXL).
• Strong understanding of digital design fundamentals, clock domain crossing (CDC), and power-aware design (UPF/CPF).
• Proficient with industry-standard EDA tools for simulation, synthesis, and static timing analysis.

Responsibilities

• Lead end-to-end design of complex digital Soft IP cores using Verilog/SystemVerilog.
• Mentor junior and senior design engineers; provide technical direction on RTL coding standards and PPA optimization.
• Collaborate with verification teams to ensure 100% functional coverage and develop testbenches (UVM/SystemVerilog) and formal verification methodologies.
• Work with physical design teams to provide constraints and guidance for synthesis, timing closure, and layout integration.
• Act as the primary technical contact for clients integrating IP, providing support for integration, debugging, and post-silicon validation.
• Drive adoption of advanced EDA tools and automated design flows to improve design cycle efficiency and product quality.

Skills

Verilog/SystemVerilog

AMBA AXI/AHB/APB

PCIe

DDR/LPDDR

CDC & UPF/CPF

EDA tools (Synopsys Cadence Mentor)

Leadership & mentoring

Client communication

Education

Bachelor's or Master's in Electrical/ Electronics Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Job description

Oppstar Technology is seeking a Principal Engineer for Soft IP to lead design, verification, and delivery of synthesizable RTL cores for complex SoCs. You will bridge architectural concepts and silicon realization, mentoring engineers and coordinating with verification and physical design teams.

The ideal candidate has 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog skills, and deep knowledge of standard bus protocols (AXI, PCIe, DDR).