Principal Soft IP Engineer

Oppstar Technology; Penang; On-site; MYR 180,000 - 240,000; Full time

Job summary

Oppstar Technology is seeking a Principal Engineer for Soft IP to lead design, verification, and delivery of synthesizable RTL cores for complex SoCs. You will bridge architectural concepts and silicon realization, mentoring engineers and coordinating with verification and physical design teams.

The ideal candidate has 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog skills, and deep knowledge of standard bus protocols (AXI, PCIe, DDR).

Qualifications

• 10+ years of experience in ASIC/SoC design with focus on IP development (Soft IP/Digital Design).
• Expertise in Verilog / SystemVerilog and hardware description languages.
• In-depth knowledge of standard bus protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR/LPDDR, CXL).
• Strong understanding of digital design fundamentals, clock domain crossing (CDC), and power-aware design (UPF/CPF).
• Proficient with industry-standard EDA tools for simulation, synthesis, and static timing analysis.

Responsibilities

• Lead end-to-end design of complex digital Soft IP cores using Verilog/SystemVerilog.
• Mentor junior and senior design engineers; provide technical direction on RTL coding standards and PPA optimization.
• Collaborate with verification teams to ensure 100% functional coverage and develop testbenches (UVM/SystemVerilog) and formal verification methodologies.
• Work with physical design teams to provide constraints and guidance for synthesis, timing closure, and layout integration.
• Act as the primary technical contact for clients integrating IP, providing support for integration, debugging, and post-silicon validation.
• Drive adoption of advanced EDA tools and automated design flows to improve design cycle efficiency and product quality.

Skills

Verilog/SystemVerilog

AMBA AXI/AHB/APB

PCIe

DDR/LPDDR

CDC & UPF/CPF

EDA tools (Synopsys Cadence Mentor)

Leadership & mentoring

Client communication

Education

Bachelor's or Master's in Electrical/ Electronics Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Job description

As a Principal Engineer for Soft IP, you will play a critical leadership role in the development of high-performance, reusable semiconductor Intellectual Property (IP) cores. You will bridge the gap between architectural theory and final silicon implementation. Your primary responsibility is to lead the design, verification, and delivery of synthesizable RTL (Register Transfer Level) that serves as the building block for clients' complex SoC (System-on-Chip) designs.

Key responsibilities

Lead the end-to-end design of complex digital Soft IP cores using Verilog/SystemVerilog. Ensure designs are modular, configurable, and optimized for multiple foundry nodes and process technologies.

Mentor junior and senior design engineers. Provide technical direction on RTL coding standards, power/performance/area (PPA) optimization, and design-for-reuse strategies.

Collaborate with verification teams to ensure 100% functional coverage. Define and oversee the development of testbenches (UVM/SystemVerilog) and formal verification methodologies to ensure first-time-right silicon.

Work closely with physical design teams to provide necessary constraints (SDC) and guidance for synthesis, timing closure, and layout integration.

Act as the primary technical point of contact for clients integrating IP, providing support for integration, debugging, and post-silicon validation.

Drive the adoption of advanced EDA tools and automated design flows to improve design cycle efficiency and product quality.

About you

Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related fields.

10+ years of experience in ASIC/SoC design, with a strong focus on IP development (Soft IP/Digital Design).

Expertise in Verilog / SystemVerilog and hardware description languages.

In-depth knowledge of standard bus protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR/LPDDR, CXL).

Strong understanding of digital design fundamentals, clock domain crossing (CDC), and power-aware design (UPF/CPF).

Proficient with industry-standard EDA tools (Synopsys, Cadence, or Mentor Graphics) for simulation, synthesis, and static timing analysis.

Proven ability to lead technical teams, manage client expectations, and communicate complex technical concepts clearly.

Unlock job insights

Hirer responsiveness Salary match Number of applicants

Consumer Electronics Manufacturing 51-100 employees

Oppstar Technology was founded in 2014 in the heart of Penang. In a short span of just 6 years, we have managed to grow and provide satisfaction to our clients with our wholesome design services. Currently, we are able to take full charge of development and One-Stop Shop IC design services from the beginning to the end – all the way to the tape-out processes. Our thorough design services and committed technical support has enable Oppstar to assist clients achieve important milestones during crucial times.

Oppstar Technology has established partnership with top semiconductor companies and key foundries to provide cutting edge technology node design solutions in ASIC and FPGA to our valued customers. Currently, we have successfully delivered a number of complete projects for our key clients, ranging from 55nm to 14nm deep sub-micron process technology nodes physical design and implementation. To ensure value added product development and services, Oppstar Technology prioritizes quality and timeliness in everything we do.

Oppstar Technology was founded in 2014 in the heart of Penang. In a short span of just 6 years, we have managed to grow and provide satisfaction to our clients with our wholesome design services. Currently, we are able to take full charge of development and One-Stop Shop IC design services from the beginning to the end – all the way to the tape-out processes. Our thorough design services and committed technical support has enable Oppstar to assist clients achieve important milestones during crucial times.

Oppstar Technology has established partnership with top semiconductor companies and key foundries to provide cutting edge technology node design solutions in ASIC and FPGA to our valued customers. Currently, we have successfully delivered a number of complete projects for our key clients, ranging from 55nm to 14nm deep sub-micron process technology nodes physical design and implementation. To ensure value added product development and services, Oppstar Technology prioritizes quality and timeliness in everything we do.