Senior FPGA IP Design Engineer - Wireless Soft IP RTL

Altera; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera in Penang, Malaysia, is seeking a Senior IP Design Engineer specializing in FPGA Soft IP RTL development to design, develop, and verify wireless IP cores for FPGA platforms in collaboration with system architects and verification teams.

You will work across architecture, RTL design, verification and hardware validation, contributing to high-speed interfaces and FPGA constraints, with a focus on quality, performance, and timely delivery.

Qualifications

• Bachelor's degree in Electrical, Electronics, Computer Engineering or equivalent.
• Proficiency in Verilog/SystemVerilog, RTL design coding.
• Experience in FPGA, custom IC or ASIC design with design/verification focus.

Responsibilities

• Design, develop and verify wireless IP cores for FPGA platforms.
• Collaborate with system architects, verification engineers and software teams.
• Ensure RTL design meets timing, constraints and quality standards.

Skills

Verilog/SystemVerilog

RTL design coding

FPGA

Communication skills

Problem solving

Education

Bachelor's degree in Electrical, Electronics, Computer Engineering or equivalent

Tools

Synopsys VCS

Questa

Modelsim

Perl

Python

Job description

Altera in Penang, Malaysia, is seeking a Senior IP Design Engineer specializing in FPGA Soft IP RTL development to design, develop, and verify wireless IP cores for FPGA platforms in collaboration with system architects and verification teams.

You will work across architecture, RTL design, verification and hardware validation, contributing to high-speed interfaces and FPGA constraints, with a focus on quality, performance, and timely delivery.