Staff Silicon Design Engineer - PCIe IP Verification

AMD; George Town; On-site; MYR 180,000 - 300,000; Full time

Job summary

AMD in Penang, Malaysia, seeks an experienced ASIC design verification engineer to join the PCIe IP verification team. You will work with architects and designers on verification infrastructure, develop testbenches and verify new PCIe IP features end-to-end.

The role requires 8+ years of ASIC verification experience, leadership capability, and strong knowledge of UVM, SystemVerilog and Verilog. Familiarity with PCIe and high-speed IO is a plus; fluent English is essential for global

Qualifications

• Solid ASIC design verification experience and 8+ years in ASIC tape-out projects.
• Experience leading teams and testbench architecture.
• Strong knowledge of UVM, SystemVerilog and Verilog.
• PCIe knowledge preferred; Serdes PHY or other IO is a plus.

Responsibilities

• Develop and update infrastructure and environment for IP level design verification.
• Collaborate with Design and Architecture to develop new verification components.
• Define verification plans and drive closure for PCIe SS IP features.

Skills

Communication skills

Team leadership

English proficiency (written)

Education

Bachelor's/Master's in Computer/Electrical Engineering

Tools

UVM

SystemVerilog

Verilog

Job description

AMD in Penang, Malaysia, seeks an experienced ASIC design verification engineer to join the PCIe IP verification team. You will work with architects and designers on verification infrastructure, develop testbenches and verify new PCIe IP features end-to-end.

The role requires 8+ years of ASIC verification experience, leadership capability, and strong knowledge of UVM, SystemVerilog and Verilog. Familiarity with PCIe and high-speed IO is a plus; fluent English is essential for global