Senior Verilog RTL SoC Engineer

Bitdeer (NASDAQ: BTDR); Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Bitdeer, a global technology company, is hiring in Penang, Malaysia for an experienced SoC/IC design engineer. The role focuses on Verilog RTL for SoC sections, IP integration, and optimization across synthesis, timing, power, and floorplanning.

Collaboration with IP teams and verification is required. The ideal candidate has a Master’s or Bachelor’s in Electrical or Computer Engineering with 5+ years in semiconductor R&D, deep SoC knowledge, and proficiency in scripting and FPGA prototyping.

Qualifications

• Master’s degree or Bachelor’s degree in Electrical Engineering or Computer Engineering with 5 years or more in a semiconductor or high technology R&D experience would be appreciated.
• Verilog RTL development experience with industry-standard tools in an SoC environment.
• Strong understanding of SoC architecture and logic design.
• Strong problem-solving and debugging skills.
• Knowledge of clocking, reset sequences, power-up sequences, and power management.
• Exposure to verification methods.
• Comfort with scripting languages (Perl, Shell, TCL) to automate design tasks.
• Knowledge of emulation and FPGA prototyping is preferred.

Responsibilities

• Implement Verilog RTL for various sections of SoC.
• Work with IP engineers to integrate IPs to the SoC.
• Support synthesis, timing closure, power reduction, and floorplanning efforts to optimize performance and efficiency.
• Contribute to design verification & emulation and assist in debugging issues across pre-silicon and post-silicon stages.

Skills

Verilog RTL

SoC architecture

Debugging

Scripting (Perl, Shell, TCL)

Emulation/FPGA prototyping

Education

Master’s or Bachelor’s in Electrical/Computer Engineering

Job description

Bitdeer, a global technology company, is hiring in Penang, Malaysia for an experienced SoC/IC design engineer. The role focuses on Verilog RTL for SoC sections, IP integration, and optimization across synthesis, timing, power, and floorplanning.

Collaboration with IP teams and verification is required. The ideal candidate has a Master’s or Bachelor’s in Electrical or Computer Engineering with 5+ years in semiconductor R&D, deep SoC knowledge, and proficiency in scripting and FPGA prototyping.