HSIO Validation Lead — PCIe/UCIe & PHY Expert

AMD; Penang; Hybrid; MYR 180,000 - 240,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD Penang, Malaysia is seeking an HSIO Technical Lead to drive validation of high-speed interfaces (PCIe, xGMI, UAlink, IFoE, UCIe) across platforms. You will collaborate with design, signal integrity, firmware, and quality teams to define strategies and execute test plans.

The role emphasizes margining, PHY analysis, and enabling advanced interface features while mentoring junior engineers and driving automation for scalable coverage.

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering.
• Expertise in high-speed signaling and PCIe/xGMI/UCIe protocols.
• Hands-on lab validation, margining, PHY analysis, and test automation.

Responsibilities

• Define and execute validation strategies for PCIe, xGMI, UAlink, IFoE, and UCIe.
• Develop test plans for SI, protocol compliance, margining, and interoperability.
• Perform margining tests and PHY analysis to optimize interface robustness.
• Validate advanced interface features and ensure seamless integration.
• Design test cases to verify functionality, performance, and reliability.
• Identify and resolve issues with cross-functional teams.
• Drive automation and regression testing for scalable coverage.
• Collaborate with global teams to align validation goals.

Skills

High-speed signaling

Protocol standards PCIe/UAlink/UCIe

Margining & PHY analysis

Test automation & debugging

Leadership & communication

Education

Bachelor's or Master’s in Electrical/Computer Engineering

Tools

Oscilloscopes

Validation tools

Job description

AMD Penang, Malaysia is seeking an HSIO Technical Lead to drive validation of high-speed interfaces (PCIe, xGMI, UAlink, IFoE, UCIe) across platforms. You will collaborate with design, signal integrity, firmware, and quality teams to define strategies and execute test plans.

The role emphasizes margining, PHY analysis, and enabling advanced interface features while mentoring junior engineers and driving automation for scalable coverage.