Principal NoC IP Micro-Architect

Altera; George Town; On-site; MYR 240,000 - 360,000; Full time

Job summary

Altera in Penang, Malaysia seeks a senior RTL/NOC designer to develop logic and RTL for Network on Chip IPs and FPGA IPs. You will define architecture features, create prototypes, simulate models, and deliver device-level bring-up support with power and timing considerations.

The role includes mentoring junior engineers, guiding the NOC team, and proactively addressing design challenges to ensure successful project delivery.

Qualifications

• Bachelor's or Master's degree in electrical or computer engineering.
• 15+ years of related experience in RTL design and FPGA IP development.
• Expertise with SystemVerilog, simulators, lint, and synthesis tools.

Responsibilities

• Develops logic design, RTL coding, and simulations for NOC IPs and FPGA IPs.
• Defines architecture/microarchitecture features and creates prototypes and models.
• Ensures power, performance, and area goals through RTL implementation and verification.
• Reviews verification plans and guides corrective actions for RTL tests.
• Mentors team members and oversees the NOC team to ensure on-time delivery.

Skills

Leadership

Mentoring

Communication

Problem solving

Team collaboration

Education

Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering

Tools

SystemVerilog

VCS/Synopsys simulators

RTL lint

Synthesis

C/C++

Python

TCL

Unix Shell

CDC/DFT

Timing constraints verification

Job description

Job Details: Job Description:

Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Creates prototypes, simulates models, and specifies systems requirements. Prepares and designs logic diagrams and codes for implementing system design and test specifications. Delivers software models for device level bring up, including user visible functionality, timing, and power. Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team. Strong understanding of the design methodology & advance EDA tools like timing constrains verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development as well as deploying automation & AI to enhanced the development efficiency. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. As a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.

Qualifications:

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
• Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
• Experience in FPGA design and programming is a plus.
• Experience in RTL validation is a plus.
• Experience in development of Network on Chip IPs.
• Experience with the usage of AI with development process for high efficiency development would be a great plus.
• Ability to work with different teams, good communication and problem-solving skills.

Job Type: Regular Shift: Shift 1 (Malaysia) Primary Location: Penang 15, Penang, Malaysia Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera Altera: Accelerating Innovators

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.