ISP ASIC Design Engineer – RTL, PPA & Verification

XPENG; Kuala Lumpur; On-site; MYR 90,000 - 140,000; Full time

Benefits offered by this job

Interesting job at XPENG

Large internal/external contact

Salary incl. pension with bonus

Involvement in EV brand growth in EMEA

Job summary

XPENG seeks an experienced RTL Design engineer to contribute to ISP module RTL and support dataflow, line buffers, and caching decisions.

You will collaborate with algorithm and DV teams to ensure fixed-point alignment with the reference model and assist silicon bring-up and image-quality debugging. A strong Verilog/SystemVerilog background and hands-on EDA tool experience are required.

Qualifications

• BS or above in Microelectronics / EE / Communications / CS or related field.
• 3+ years of digital IC front-end experience, including 1+ year on ISP modules.
• Proficient in Verilog / SystemVerilog; familiar with SVA.
• Hands-on with mainstream EDA tools.
• Familiar with AMBA protocols/ISP Domain
• Solid understanding of the camera imaging pipeline and the role of each stage.
• Familiar with mainstream CFA patterns and their processing differences.
• Able to discuss fixed-point precision, error accumulation and line-buffer trade-offs with algorithm engineers.

Responsibilities

• ISP Module RTL Design: Design and implement RTL for blocks in the ISP pipeline.
• Contribute to dataflow, line buffer and caching decisions; support PPA trade-offs.
• Work with the algorithm team on fixed-point transformations and alignment with reference model.
• Collaborate with DV on verification plan and silicon bring-up; assist in image-quality debug and RTL ECOs.
• Perform code review, Lint, CDC/RDC and basic low-power checks; deliver module-level design documentation.

Skills

RTL design

Fixed-point analysis

Camera imaging pipeline

Education

Bachelor's degree in Microelectronics / EE / Communications / CS

Tools

Verilog/SystemVerilog

SVA

EDA tools

AMBA protocols

Job description

XPENG seeks an experienced RTL Design engineer to contribute to ISP module RTL and support dataflow, line buffers, and caching decisions.

You will collaborate with algorithm and DV teams to ensure fixed-point alignment with the reference model and assist silicon bring-up and image-quality debugging. A strong Verilog/SystemVerilog background and hands-on EDA tool experience are required.