Senior FPGA IP Design Engineer - Wireless RTL Cores

Altera; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera in Penang, Malaysia, seeks a Senior IP Design Engineer specializing in FPGA Soft IP RTL development to design, develop and verify wireless IP cores for FPGA platforms.

You will collaborate with system architects, verification engineers and software teams to deliver reliable, high-performance wireless solutions. Candidates should hold a Bachelor's degree in Electrical/Electronics/Computer Engineering and have experience with Verilog/SystemVerilog and FPGA design.

Qualifications

• Bachelor's degree in Electrical, Electronics, Computer Engineering or equivalent.
• Proficiency in Verilog/SystemVerilog; RTL design coding.
• Experience in FPGA/ASIC/IC design across architecture, design, validation, or product.
• Familiarity with simulation and verification tools (Synopsys VCS, Questa, Modelsim).
• Knowledge of high-speed interfaces (Ethernet, CPRI, eCPRI) and O-RAN familiarity.
• Understanding timing closure and clock domain crossing.
• Familiarity with Perl, TCL, Python and shell scripts.
• Strong communication; accountability and teamwork.
• Analytical and proactive problem-solving mindset.

Responsibilities

• Design, develop, and verify wireless IP cores for FPGA platforms.
• Collaborate with system architects, verification engineers, and software teams.
• Participate in high-level product specifications, RTL implementation and hardware validation.

Skills

Verilog/SystemVerilog

RTL design

FPGA design

Communication

Education

Bachelor's degree in Electrical/Electronics/Computer Engineering

Tools

Synopsys VCS

Questa

Modelsim

Job description

Altera in Penang, Malaysia, seeks a Senior IP Design Engineer specializing in FPGA Soft IP RTL development to design, develop and verify wireless IP cores for FPGA platforms.

You will collaborate with system architects, verification engineers and software teams to deliver reliable, high-performance wireless solutions. Candidates should hold a Bachelor's degree in Electrical/Electronics/Computer Engineering and have experience with Verilog/SystemVerilog and FPGA design.