Senior FPGA IP Solution Design Engineer

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 60,000 - 90,000; Full time

Job summary

754 Altera Semiconductor Technology (M) Sdn. Bhd. seeks a Senior IP Design Engineer to focus on FPGA Soft IP RTL development. You will design and verify wireless IP cores, collaborating with system architects and software engineers to deliver cutting-edge wireless solutions.

The ideal candidate holds a Bachelor's degree in Electrical or Computer Engineering and possesses expertise in Verilog/System Verilog. Familiarity with FPGA design and verification tools is essential.

Qualifications

• Bachelor's degree in a relevant field.
• Proficiency in Verilog/System Verilog and RTL design coding.
• Experience in FPGA or ASIC design with a solid architecture background.
• Familiarity with simulation tools like Synopsy VCS or Questa.
• Knowledge of Ethernet and CPRI interfaces.
• Understanding of O-RAN architectures is a plus.

Responsibilities

• Design, develop, and verify wireless IP cores for FPGA platforms.
• Collaborate with system architects and software teams.
• Participate in high-speed protocol IP development.

Skills

Verilog/System Verilog and RTL design coding

FPGA design or ASIC design

Simulation and verification tools

Knowledge of high-speed serial interfaces

Understanding of timing closure and FPGA constraints

Familiarity with Python and shell scripts

Education

Bachelor's degree in Electrical, Electronics, Computer Engineering or equivalent

Job description

Altera offers a large selection of intellectual property IP cores optimized for Altera FPGA devices, all of which are developed for highest performance, lowest cost, ease of use and fastest time-to-market.

The FPGA IP System & Solution Engineering group is responsible for High Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA emulation prototyping and hardware validation.

In the role of Senior IP Design Engineer specializing in FPGA Soft IP RTL development, you will be responsible for designing, developing, and verifying wireless IP cores for FPGA platforms, while working closely with system architects, verification engineers, and software teams to deliver reliable and high-performance wireless solutions.

Qualifications

• Bachelor's degree in Electrical, Electronics, Computer Engineering or equivalent.
• Proficiency in Verilog/System Verilog and RTL design coding.
• Experience in FPGA, custom IC or ASIC design, demonstrating excellence in architecture, design, validation or product development.
• Familiarity with simulation and verification tools such as Synopsy VCS, Questa, Modelsim, etc.
• Knowledge of high-speed serial interfaces such as Ethernet, CPRI, and eCPRI.
• Understanding of O-RAN architectures is a strong plus.
• Understanding of timing closure, clock domain crossing, and FPGA constraints.
• Familiarity with Perl, TCL, Python and shell scripts is a plus.
• Strong written and verbal communication skills for collaboration with cross-functional teams.
• Strong analytical and problem-solving skills, with a proactive mindset that promotes innovation and teamwork.
• Demonstrates fundamental values such as accountability, integrity and a winning mindset.

Job Details

• Job Type: Regular
• Shift: Shift1 (Malaysia)
• Primary Location: Penang 15, Penang, Malaysia
• Additional Locations: Posting Statement (all qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance).

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.