Senior Engineer - Memory Design

Sinergia Talents; Kuching; On-site; MYR 140,000 - 240,000; Full time

Job summary

Sinergia Talents seeks a Senior Engineer in Memory Design to contribute to an innovative team by designing SRAM and ROM blocks and developing in-house verification flows.

You will work on low power and high-performance circuits, participate in ISO26262 contexts, and collaborate with a multi-national team to deliver robust memory solutions.

Qualifications

• Master’s degree in electronics engineering or equivalent.
• Minimum 5 years of memory design experience and memory characterization.
• Proficient written and spoken English; strong communication skills.
• Experience with memory design cycle and QA processes.

Responsibilities

• Define architecture and schematic design of RAM/ROM for optimal power and performance.
• Verify leafcells and circuit blocks across PVT and compiler spaces.
• Implement memory characterization flows using NLDM/NLPM and CCS methods.
• Develop front-end views (LIB) for memory IP integration in SoC.
• Create documentation and participate in design reviews per ISO26262.

Skills

Communication

Teamwork

English writing

Analytical

Self-motivated

Education

MEng Electronics

Tools

Schematic editor

Spice simulators

Characterization tools

EDA tools

Job description

About the job Senior Engineer - Memory Design

Job Summary

We are looking for a Memory Design Engineer to contribute to a highly innovative team by designing and developing high quality SRAM and ROM. You will work with other team members on the new process design challenges. You will have the chance to create novel low power and high-performance circuits and develop in-house design and verification flows for SRAM and ROM design in the context of ISO26262.

Job Responsibilities

As a part of SRAM/ROM Design team, you would be working on

• Architecture definition and schematic design of RAM and ROM compilers to get the most optimal circuit in terms of power and performance.
• Verification of leafcells/circuit blocks including analysis of circuit behavior, timing marginalities, correct description of timing characterization intent on both pre and post layout netlist across the entire PVT space and compiler cut space.
• Implement memory characterization flows based on NLDM/NLPM and CCS characterization
• Mitigate risks through proactive design analysis
• Generate front-end views (LIB) for memory IP integration in System-on-Chip.
• Documentation and design review organization for compliant development in the context of ISO26262
• Development QA flow for design verification
• Any other assignment and role deemed appropriated might be assigned to you from time to time

Job Requirements and Qualifications

• Qualification: Master or higher in Electronics Engineering.
• Minimum 5 years of working experience in memory design and memory characterization. Exposure to complete design cycle of memory development
• Good communication skills – good level in English, written and spoken.
• Teamwork and collaboration skills, working within multi-national, multi-site team
• Open, curious in new design implementation, integrity and friendly when engaging internal/external customers.
• Self-motivated, progressive attitude, and able to work independently with minimum supervision
• Excellent writing and reporting skills with strong communication and analytical skills
• Able to learn quickly, self-driven and results-oriented
• Experience in using EDA tools for schematic entry and advanced transistor level simulators. Proven experience on transistor-level circuit design and circuit behavior analysis
• Solid understanding of device physics and process
• Knowledge of industry standard circuit simulation and design tools
• Deep background of the design, verification, and characterization of memory
• Solid understanding on generating performance/power/margin data of memory, validation of data and QA process
• Hands‑on experience running SPICE simulation, and capability to adapt to new simulation tools
• Experience in Programming language, such as, Perl, Python, Tcl, and automation methods/algorithms is an advantage
• In-depth understanding of circuit fundamentals with a good exposure to digital and analog circuit design is a must. Strong experience to Memory design and characterization and associated EDA tools (Schematic editor, Spice Simulators, Characterization Infrastructure etc.).