Memory Validation

UST Malaysia; Seberang Perai; On-site; MYR 60,000 - 80,000; Full time

Job summary

UST Malaysia is seeking a memory validation engineer to lead platform-level memory validation efforts in Penang. You will drive DDR test plans and collaborate closely with silicon design and cross-site memory teams to ensure thorough validation across products.

The role emphasizes hands-on debugging of DDR interfaces, reading schematics, and using Python/Ruby/Perl for automation. Strong communication and program management skills are essential in a fast-paced environment.

Qualifications

• Develop and execute platform level electrical and functional test plans for memory subsystems.
• DDR/GDDR memory test experience on electronic components such as processors is a big plus.
• Extensive hands-on debugging of I/O interfaces such as DDR.
• Ability to read schematics and layout documentation.
• Strong written and oral communication skills.
• Familiar with Python, Ruby, and Perl languages.
• Self-motivated with program management capability.

Responsibilities

• Focus on memory sub-system validation.
• Provide DDR technical leadership in test & validation.
• Develop and execute system level memory sub-system validation test plans across products.
• Collaborate with silicon design and cross-site memory teams on test execution & debugging.
• Work with validation, design, firmware, software, and automation teams for integration and validation.
• Deliver professional project reports and highlight risks with mitigation plans.
• Use data analysis to optimize processes, efficiency, and quality.
• Identify opportunities to improve validation processes and automation.

Skills

Memory validation

DDR testing

Platform test plans

Python

Ruby

Perl

I/O interface debugging

Program management

Data analysis

Communication

Education

BE or MSc in related field

Job description

• Focused on memory sub-system validation.
• Provides DDR technical leadership in the development of new test & validation
• Develop and execute system level memory sub-system validation test plans across products.
• Closely interacts with silicon design and cross-site memory teams in test execution & debug.
• Work closely with validation leader, design, firmware, and software, automation teams to ensure seamless integration and validation
• Deliver professional project reports to management, highlight risk in time with solution plans.
• Smart and initiative on data analysis to consistently optimize process, efficiency, and quality improvement.
• Identify opportunities to improve validation processes, automation tools, and methodologies to enhance efficiency and effectiveness.

Preferred Experience

• Demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR/GDDR Memory test experience on electronic components such as Processors would be considered a big plus.
• Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR.
• Familiar with signal measurement, reading schematics and layout documentation
• Requires good written and oral communication skills.
• Familiar with Python, Ruby, Perl language.
• Self-Motivated with program management skillset.

Academic Credentials

• Requires BE+ or master's degree with 5+ years' experience.