Senior Electronics Engineer: PD, Timing & EDA Specialist

Quest Global; Bayan Lepas; On-site; MYR 180,000 - 240,000; Full time

Benefits offered by this job

Competitive Benefit

Job summary

Quest Global is seeking a senior Electronics Engineer with 5-10 years of PD experience in Physical Design, RTL-to-GDS flow, and advanced timing closures. The role expects expertise in static timing, power analysis, and the Innovus toolchain, with scripting in TCL/SHELL/PYTHON to automate PD flows.

Candidates should be adept with FinFET and dual-patterning nodes (16/14/10/7/5/3nm) and hold a bachelor’s degree in Electronics Engineering.

Qualifications

• 5-10 years’ experience with bachelor’s degree in Electronics Engineering or equivalent.
• Must have experience in Physical Design and PD-flow from RTL to GDS.
• Knowledge of Static Timing Analysis, Power Analysis and Innovus.
• Hands-on experience with PD-flow/EDA-tools scripts using TCL/SHELL/PYTHON.
• Experience in PD metrics dashboards for QOR tracking is a plus.
• Experience in STA constraints for timing closure and clock strategies.
• Experience in FinFET and Dual Patterning nodes (16/14/10/7/5/3nm).
• Experience with various clock implementation strategies for latency/ skew targets.

Responsibilities

• 5-10 years’ experience with bachelor’s degree in Electronics Engineering or equivalent.
• Experience in Physical Design with PNR flow from RTL to GDS flow,
• Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.
• Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
• Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
• Experience in modifying STA constraints to check timing closure feasibility
• Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

Skills

PD flow

EDA tools scripts

TCL

SHELL

PYTHON

Static Timing Analysis

Power Analysis

Innovus

FinFET

Dual Patterning

Education

Bachelor's degree in Electronics Engineering

Tools

Innovus

TCL

SHELL

Python

Job description

Quest Global is seeking a senior Electronics Engineer with 5-10 years of PD experience in Physical Design, RTL-to-GDS flow, and advanced timing closures. The role expects expertise in static timing, power analysis, and the Innovus toolchain, with scripting in TCL/SHELL/PYTHON to automate PD flows.

Candidates should be adept with FinFET and dual-patterning nodes (16/14/10/7/5/3nm) and hold a bachelor’s degree in Electronics Engineering.