Hybrid Front-End Silicon Design Engineer (ASIC/SoC)

AMD; Penang; Hybrid; MYR 120,000 - 180,000; Full time

Job summary

AMD in Penang is seeking a highly motivated Front End Integration Silicon Design Engineer to drive next generation ASIC/SoC development, combining RTL design with AI/ML enhanced workflows.

You will collaborate with global teams, tackle timing, power, and netlist quality, and contribute to front-end flow, from RTL to netlist ready for physical design.

Experience in Verilog RTL, front-end EDA tools, and Unix/Linux scripting is expected; 8–10 years in large digital ASIC projects preferred.

Qualifications

• Experience with Verilog RTL design in large digital ASIC projects.
• Strong collaboration across sites/time zones is expected.
• Solid foundation in ASIC/SoC design and verification is required.
• Knowledge of AI/ML techniques for engineering workflows is a plus.

Responsibilities

• Front-end chip implementation from RTL to netlist for physical design.
• Develop ASIC design methodology and interface with EDA vendors.
• Ensure CDC/Lint, timing closure, and power optimization with PD team.

Skills

Verilog RTL design

ASIC/SoC design

Front-end EDA tools

Unix/Linux scripting

Low power design

Team collaboration

Education

Bachelor's or Master's in Computer/Electrical & Electronics Engineering

Tools

Design Compiler

PrimeTime

Conformal

VSI/VC-static

Formality

Job description

AMD in Penang is seeking a highly motivated Front End Integration Silicon Design Engineer to drive next generation ASIC/SoC development, combining RTL design with AI/ML enhanced workflows.

You will collaborate with global teams, tackle timing, power, and netlist quality, and contribute to front-end flow, from RTL to netlist ready for physical design.

Experience in Verilog RTL, front-end EDA tools, and Unix/Linux scripting is expected; 8–10 years in large digital ASIC projects preferred.