Senior Digital Design Architect — SoCs/ASICs

SkyeChip Berhad; Penang; On-site; MYR 120,000 - 180,000; Full time

Benefits offered by this job

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Job summary

SkyeChip is seeking a senior IC design engineer to architect, design, and verify complex digital IPs and SOC subsystems for ASIC/FPGA products in Malaysia. You will collaborate with system architects, verification, and physical design teams to deliver high-performance RTL implementations.

You'll lead design reviews, support documentation, and help shape roadmaps for sensor IPs, while ensuring RTL correctness and robust verification across the SoC flow.

Qualifications

• Bachelor’s or Master’s degree in Electronic Engineering.
• 5–10+ years of experience in ASIC/FPGA digital design.
• Strong knowledge of RTL design using SystemVerilog/Verilog.
• Deep understanding of SoC design flow, including synthesis, timing, power, and verification.
• Familiar with AMBA bus protocols (AXI/AHB/APB).
• Experience with EDA tools (Synopsys, Cadence, Mentor).
• Excellent debugging and problem-solving skills.
• Strong communication and documentation abilities.

Responsibilities

• Architect with system engineers to perform:-
• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.
• Work with architects on complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products
• Conduct design reviews and support in documentation.
• Support in the roadmap formulation for the sensor IPs.
• Support view generation engineers to verify the correctness of the Ips views.

Skills

SystemVerilog/Verilog

RTL design

SoC design flow

Debugging

Problem-solving

Communication

Documentation

Education

Bachelor’s or Master’s degree in Electronic Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Job description

SkyeChip is seeking a senior IC design engineer to architect, design, and verify complex digital IPs and SOC subsystems for ASIC/FPGA products in Malaysia. You will collaborate with system architects, verification, and physical design teams to deliver high-performance RTL implementations.

You'll lead design reviews, support documentation, and help shape roadmaps for sensor IPs, while ensuring RTL correctness and robust verification across the SoC flow.