ASIC Design Verification (DV) Manager

SkyeChip Berhad; Penang; On-site; MYR 180,000 - 320,000; Full time

Job summary

SkyeChip Berhad is seeking an experienced ASIC DV Manager to lead and grow the verification engineering team, owning full verification methodology and execution quality across multiple concurrent customer engagements.

This hands‑on technical leadership role involves reviewing UVM architectures, defining coverage closure strategies, writing constraint blocks, and presenting risk and schedule status to customers with confidence.

Qualifications

• 10+ years of hands‑on ASIC functional verification experience, with 3+ years in a lead or management capacity.
• Deep expertise in SystemVerilog and UVM; able to architect and critically review complex agent, scoreboard, and coverage collector implementations.
• Strong command of coverage‑driven and constraint‑random verification methodology.
• Proficiency with industry‑standard simulation tools: Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Hands‑on experience with formal property verification: JasperGold, Questa Formal, or equivalent.
• Experience with CDC/RDC analysis flows: SpyGlass, Questa CDC, or equivalent.
• Python or Perl scripting for regression automation, coverage analysis, and flow integration.

Responsibilities

• Build, manage, and mentor a team of DV engineers spanning RTL simulation, formal verification, and emulation.
• Define team structure, hiring roadmap, and individual competency development plans.
• Conduct rigorous technical reviews and drive engineering excellence standards across the group.
• Partner with Physical Design, RTL Design, and Project Management leads on integrated project execution.
• Define regression infrastructure strategy including farm utilization, CI integration, and nightly regression hygiene.
• Interface directly with customers on DV scope definition, milestone reviews, and bug triage.

Job description

Role Summary

SkyeChip is a turnkey ASIC design services company delivering customer silicon from RTL to GDSII across advanced process nodes. We are looking for an experienced ASIC DV Manager to lead and grow our verification engineering team, owning full verification methodology and execution quality across multiple concurrent customer engagements.

This is a hands‑on technical leadership role. The right candidate can review a UVM testbench architecture, debate coverage closure strategy, and write a constraint block — then step into a customer review to present risk and schedule status with equal confidence.

Key Responsibilities

• Build, manage, and mentor a team of DV engineers spanning RTL simulation, formal verification, and emulation
• Define team structure, hiring roadmap, and individual competency development plans
• Conduct rigorous technical reviews and drive engineering excellence standards across the group
• Partner with Physical Design, RTL Design, and Project Management leads on integrated project execution

2. Technical Ownership

• Define and own SkyeChip's DV methodology: UVM‑based simulation, formal property verification, CDC/RDC analysis, low‑power verification, and emulation flows
• Establish and enforce coverage closure criteria — functional, code, and toggle — as part of tapeout sign‑off
• Drive adoption of reusable VIP and testbench IP assets across concurrent projects
• Review and approve DV architecture and verification plans at project kickoff
• Lead or support debug of complex design issues at block and SoC integration level

3. Project Execution

• Develop and maintain DV schedules, resource plans, and risk registers across all active engagements
• Interface directly with customers on DV scope definition, milestone reviews, and bug triage
• Define regression infrastructure strategy including farm utilization, CI integration, and nightly regression hygiene
• Participate in tapeout readiness reviews and sign‑off gate decisions

Qualifications

• B.Eng. or M.Eng. in Electrical Engineering, Computer Engineering, or equivalent discipline
• Candidates with non‑traditional academic backgrounds but exceptional engineering track records will be considered
• 10+ years of hands‑on ASIC functional verification experience, with 3+ years in a lead or management capacity
• Track record of delivering silicon verification sign‑off on production ASICs
• Deep expertise in SystemVerilog and UVM — able to architect and critically review complex agent, scoreboard, and coverage collector implementations
• Strong command of coverage‑driven and constraint‑random verification methodology
• Proficiency with industry‑standard simulation tools: Synopsys VCS, Cadence Xcelium, or Mentor Questa
• Hands‑on experience with formal property verification: JasperGold, Questa Formal, or equivalent
• Experience with CDC/RDC analysis flows: Synopsys SpyGlass, Mentor Questa CDC, or equivalent
• Python or Perl scripting for regression automation, coverage analysis, and flow integration

PREFERRED QUALIFICATIONS

• Experience with FPGA‑based emulation or prototyping platforms (Cadence Palladium, Mentor Veloce, or equivalent)
• Low‑power verification experience: UPF/CPF‑aware simulation and power intent verification
• Protocol VIP expertise in one or more of: PCIe, DDR5/LPDDR5, USB, AMBA (AXI/AHB/CHI), I3C
• Exposure to mixed‑signal / AMS co‑simulation verification flows
• Prior experience in an ASIC design services environment with multi‑customer, concurrent project delivery
• Familiarity with advanced process nodes: 16/12nm, 7nm, N5/N3

Consumer Electronics Manufacturing 101-1,000 employees

About SkyeChip

We set our eyes to be a global IC company powered by Malaysian talents, focusing on delivering cutting edge IPs and ASIC solutions to accelerate AI Deep Learning and High‑Performance Computing systems.

We are looking for high aiming IC design engineers to join us and seize the golden startup opportunity. We have a high growth market and keen customers waiting for our technology solutions. We value innovation, different perspectives, ideas, and we are committed to help you reach your full potential.

We offer competitive pay and benefits, generous stock options to share the company's success and unlimited career advancement opportunities! With Skyechip, the sky is the limit.

About SkyeChip

We set our eyes to be a global IC company powered by Malaysian talents, focusing on delivering cutting edge IPs and ASIC solutions to accelerate AI Deep Learning and High‑Performance Computing systems.

We are looking for high aiming IC design engineers to join us and seize the golden startup opportunity. We have a high growth market and keen customers waiting for our technology solutions. We value innovation, different perspectives, ideas, and we are committed to help you reach your full potential.

We offer competitive pay and benefits, generous stock options to share the company's success and unlimited career advancement opportunities! With Skyechip, the sky is the limit.

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