Senior Backend Engineer - IC Design

Private Advertiser; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Private Advertiser is seeking an APR/STA senior engineer to drive digital backend tasks from netlist to GDS at TOP or block level. You will perform PR (place and route), STA, PV, and PA, and collaborate with front-end teams to fix timing and constraints.

The role requires a microelectronics background, 7+ years of experience, and strong English communication. TOP STA experience and high-speed interface familiarity are preferred. Hybrid or onsite work in Penang, Malaysia may apply.

Qualifications

• Microelectronics related major, bachelor's degree or above.
• More than 7 years of work experience.
• Familiar with the complete design process from Netlist to GDS.
• Proficient in using design tools related to Innovus/ICC2, PT/computers, lec/form, starrc/QRC, PTPX/volt, caliber.
• Experience in tapping out chips with a process size below 14nm is preferred.
• Experience in TOP P&R work is preferred (top level partition, bump assignment, RDL routing, ESD plan, feedthrough inserting, pin assignment).
• Good English reading, writing, and communication skills.

Responsibilities

• Complete digital backend work from netlist to GDS at TOP or block level.
• Perform PR (place and route), STA (static timing analysis), PV (physical verification), and PA (power analysis).
• Collaborate with digital front-end engineers to debug timing, SDC, UPF issues.
• Complete block level or TOP PD work with moderate difficulty or above pre/post mask eco.
• Collaborate with the design team to evaluate and optimize the digital area.

Skills

Digital backend design

Timing analysis

Team collaboration

Education

Bachelor's degree in Microelectronics or related field

Tools

Innovus/ICC2

Caliber

Starrc/QRC

PTPX/Volt

Job description

APR/STA senior engineers are responsible for completing the digital backend work from netlist to GDS, at the TOP or block level, including PR (place and route), STA (static timing analysis), PV (physical verification), PA (power analysis), and other tasks.

Key responsibilities

Complete digital backend work from netlist to GDS at TOP or block level

Perform PR (place and route), STA (static timing analysis), PV (physical verification), and PA (power analysis)

Collaborate with digital front-end engineers to debug issues such as timing, SDC, UPF.

Complete block level or TOP PD work with moderate difficulty or above pre/post mask eco

Collaborate with the design team to evaluate and optimize the digital area

Requirements

Microelectronics related major, bachelor's degree or above

More than 7 years of work experience

Familiar with the complete design process from Netlist to GDS

Proficient in using one or several sets of design tools related to Innovus/ICC2, PT/computers, lec/form, starrc/QRC, PTPX/volt, caliber

Experience in successfully tapping out chips with a process size below 14nm is preferred

Experience in working with low-power design chips is preferred

Experience in TOP P&R work is preferred (top level partition, bump assignment, RDL routing, ESD plan, feedthrough inserting, pin assignment)

Priority given to those with TOP STA experience

Equipped with PCIE, DDR and other high-speed interface P&R experience is preferred

Good English reading, writing, and communication skills

Possess innovative ability and team spirit