Physical Design Engineer - Netlist to GDSII, Timing Signoff

Agensi Pekerjaan Eternity Sdn Bhd; Bayan Lepas; On-site; MYR 90,000 - 140,000; Full time

Job summary

Agensi Pekerjaan Eternity Sdn Bhd is seeking experienced Physical Design Engineers to join its semiconductor engineering team. The role focuses on block-level and full-chip physical implementation from netlist through GDSII/tape-out, with ownership of timing closure, physical verification and sign-off activities.

You will work on floor planning, power planning, placement, CTS, routing, and timing closure across multiple modes and corners, collaborating with STA, RTL, DFT, verification and other

Qualifications

• Bachelor's degree in Electrical & Electronic Engineering or related field.
• 4+ years of experience in engineering or physical design.
• Experience RTL/netlist-to-GDSII physical implementation.
• Experience with advanced/low technology nodes.
• Strong analytical and problem-solving skills.

Responsibilities

• Own and execute block-level and/or full-chip Physical Design from netlist to GDSII.
• Perform Floor planning, Power planning, Placement and optimization, CTS, Routing and Post-route optimization.
• Drive timing closure across multiple modes and corners (MCMM).
• Analyze and resolve Timing violations, Signal Integrity, Power issues and Physical design violations.
• Perform DRC/LVS and physical verification; ensure signoff quality.
• Perform IR Drop and EM analysis.
• Collaborate with STA, RTL, DFT, Verification and other teams.
• Support tape-out and customer deliverables.
• Participate in design reviews and contribute to flow improvements.
• Provide guidance to junior engineers (senior level).

Skills

Timing closure

Cross-functional collaboration

Analytical thinking

Education

Bachelor's degree in Electrical & Electronic Engineering or related field

Tools

GDSII

Job description

Agensi Pekerjaan Eternity Sdn Bhd is seeking experienced Physical Design Engineers to join its semiconductor engineering team. The role focuses on block-level and full-chip physical implementation from netlist through GDSII/tape-out, with ownership of timing closure, physical verification and sign-off activities.

You will work on floor planning, power planning, placement, CTS, routing, and timing closure across multiple modes and corners, collaborating with STA, RTL, DFT, verification and other