Physical design

ThunderSoft; Seberang Perai; On-site; MYR 60,000 - 90,000; Full time

Job summary

ThunderSoft is seeking an adaptive Physical Design Engineer in Penang, Malaysia to drive full-chip floorplanning, physical implementation, timing closure, and power optimization for complex SoC designs.

You will lead tapeout activities and collaborate across geographies. Candidate should have hands-on experience with floorplanning, CTS/RT, and low-power design methodologies, with strong scripting skills in TCL, Python, or Perl.

Qualifications

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.
• Experience in full-chip floorplanning, synthesis, place-and-route, timing closure and power optimization.
• Proficiency with EDA flows and scripting languages (TCL, Python, Perl).
• Strong communication and collaboration across geographies and disciplines.

Responsibilities

• Extensive hands-on experience in floorplanning, placement, CTS, routing, timing closure and physical verification.
• Proficient in timing and SDC constraint generation and management; debugging skills.
• Understanding of low-power design methodologies and voltage domain checks is advantageous.
• Tapeout experience across multiple projects.

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

Power optimization

Analytical problem-solving

Communication skills

Team collaboration

Scripting TCL

Python

Perl

Education

Bachelor’s or Master’s degree in Computer or Electrical Engineering

Tools

Design Compiler (DC)

Innovus

ICC2

STA tools

TCL scripting

Python scripting

Perl scripting

Job description

We are seeking an adaptive, self-motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive AMD’s capabilities in delivering high-performance, power-efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible for full-chip floorplanning, physical implementation, timing closure, and power optimization across complex SoC designs.

THE PERSON:

You are passionate about modern, complex processor architectures and bring deep expertise in physical implementation flows. You have experience in full-chip floorplanning, synthesis, place and route, timing closure, and power optimization. You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem-solving abilities, are eager to learn, and thrive in tackling complex design challenges.

KEY RESPONSIBILITIES:

• Extensive hands-on experience in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification
• Proficient in timing and SDC constraint generation and management; strong debugging skills are a plus
• Solid understanding of low-power design methodologies, including power-aware synthesis and place-and-route; familiarity with voltage domain checks is advantageous
• Proven experience in chip-level floorplanning, including feedthrough topology planning, repeater insertion, and top-level port/pin assignment
• Tapeout experience across multiple projects

PREFERRED EXPERIENCE:

• Proficiency in EDA tools such as Design Compiler (DC) and Innovus/ICC2
• Skilled in Static Timing Analysis (STA) tools and techniques
• Strong grasp of floorplanning and layout techniques compliant with foundry design rules
• Experience with scripting languages including TCL, Perl, and Python
• Excellent communication skills—written, verbal, and listening
• Strong interpersonal skills; adaptable, collaborative, and a dedicated team player

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering