Analog Circuit Design Engineer

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 110,000 - 160,000; Full time

Job summary

754 Altera Semiconductor Technology (M) Sdn. Bhd. is seeking experienced professionals to design, develop, and build analog circuits in George Town, Malaysia. Successful candidates will lead design tasks, collaborate with cross-functional teams, and guide junior engineers on R&D work.

The role requires a minimum of 12 years in analog/mixed-signal design, specifically with high-speed and high-voltage designs. Responsibilities include creating test plans and optimizing circuit performance.

Qualifications

• Minimum of 12 years of experience in analog/mixed-signal design.
• Hands-on experience with analog simulation and reliability tools.
• Good communication and presentation skills.

Responsibilities

• Design floorplans, perform circuit design, extract chip parameters.
• Create test plans to verify design and evaluate test results.
• Lead the design and development tasks of IP independently.

Skills

Analog circuit design

Mixed-signal design

High-speed IO design

Leadership

Team collaboration

Education

BSEE/MSEE/PhD in Electrical Engineering

Tools

Verilog

Analog simulation tools

Job description

Job Overview

Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed‑signal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross‑functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Lead and plan the design and development tasks of IP independently, guide junior engineers on R&D tasks, work with cross‑functional teams on IP development.

Responsibilities

• Design floorplans, perform circuit design, extract chip parameters, and simulate analog behavior models.
• Create test plans to verify design according to circuit and block microarchitecture specifications; evaluate test results.
• Verify functionality to optimize circuit for power, performance, area, timing, and yield goals.
• Collaborate cross‑functionally to report design progress and resolve any performance and design issues.
• Optimize performance, power, area, and reduce leakage of circuits.
• Work with architecture and layout team to design circuits for best functionality, robustness, and electrical capabilities.
• Lead and plan the design and development tasks of IP independently.
• Guide junior engineers on R&D tasks and work with cross‑functional teams on IP development.

Qualifications

• BSEE/MSEE/PhD in Electrical Engineering or equivalent with a minimum of 12 years of experience in analog/mixed‑signal design or high‑speed IO/high‑voltage IO designs including transmitter, receiver and voltage regulator.
• Direct design experience with analog and mixed‑signal circuits such as amplifiers, comparators, regulators, IO, PLL, etc.
• Nice to have: design experience of high‑speed analog and mixed‑signal design, architecture, system and integration aspects for AIB/UCIe, HBM PHYs, DDR/LPDDR/MIPI interfaces as well as LVDS/GPIO designs.
• Solid understanding of analog design trade‑offs and design for process variation and reliability in modern CMOS technologies.
• Hands‑on experience with analog simulation and reliability tools and flows.
• Understanding of Verilog, static timing analysis, UPF and related aspects of mixed‑signal design.
• Good communication and presentation skills to enable cross‑functional collaboration.
• Effective prioritization and planning, time management skills.
• Willing to work in a dynamically changing, cross‑geo environment requiring ingenuity and skills to solve issues.
• Team player – willing to work autonomously and also collaboratively.
• Leadership – expect to lead a small team of engineers for R&D task and work with cross‑functional teams independently.

Job Type

Regular

Shift and Location

Shift 1 (Malaysia)

Primary Location: Penang 15, Penang, Malaysia

Equal Employment Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.