APR Engineer - Physical Design Engineer

IntelliPro; Shah Alam; On-site; MYR 180,000 - 240,000; Full time

Job summary

IntelliPro Malaysia is seeking a technical specialist to drive back-end implementation for advanced semiconductor projects. You will lead netlist-to-GDSII flows, perform floorplanning, CTS, routing, and power planning, and collaborate with front-end and analog teams to tape-out.

The ideal candidate has 2–8 years of ASIC/mixed-signal experience, strong scripting, and proficiency in ICC2, Fusion Compiler, PrimeTime, and Innovus.

Qualifications

• Bachelor's or Master's in Electrical/Electronic Engineering or related field.
• 2–8 years in ASIC/mixed-signal physical design implementation.
• Proficiency with industry-standard EDA tools (ICC2, Fusion Compiler, PrimeTime, Innovus).

Responsibilities

• Drive netlist-to-GDSII physical implementation flows at block and full-chip levels.
• Perform floorplanning, power planning, placement, CTS, and routing.
• Conduct STA and MCMM timing closure.
• Layout optimization for timing, crosstalk, and signal integrity checks.
• Run DRC, LVS, antenna checks, and DFM sign-off.
• Perform power integrity checks including EM and IR-drop analyses.
• Develop automation scripts to streamline PnR, verification, and STA workflows.
• Collaborate with front-end, RTL, DFT, and analog/mixed-signal teams to support tape-out.

Skills

EDA tools

ASIC design

Scripting

Education

Bachelor's or Master's in Electrical Engineering

Tools

ICC2

Fusion Compiler

PrimeTime

Cadence Innovus

Job description

Jora Malaysia will close on 16th September 2026. Thank you for being with us, we are cheering you on as you continue your career journey.

We are collaborating with a specialized semiconductor design service house and global IC center in Malaysia is looking for a technical specialist to drive back-end implementation.

Description:

• Drive netlist-to-GDSII physical implementation flows at both block and full-chip levels.
• Execute floorplanning, power planning, cell placement, clock tree synthesis (CTS), and routing using standard EDA tools.
• Perform static timing analysis (STA) and drive multi-corner multi-mode (MCMM) timing closure.
• Implement layout optimization, including setup/hold timing fixes, crosstalk reduction, and signal integrity checks.
• Perform physical verification checks, including DRC, LVS, antenna rules, and DFM sign-off.
• Execute power integrity checks, covering electromigration (EM) and IR-drop analysis.
• Develop automation scripts to streamline PnR, physical verification, and STA workflows.
• Collaborate with front-end, RTL, DFT, and analog/mixed-signal teams to support final tape-out.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Microelectronics, or a related field.
• 2 to 8 years of solid hands-on experience in ASIC or mixed-signal physical design implementation.
• Proven proficiency with industry-standard EDA tools (e.g., Synopsys ICC2, Fusion Compiler, PrimeTime, or Cadence Innovus).
• Experience with advanced process nodes (e.g., 28nm, 16nm, FinFET, down to mature planar nodes for DDIC/PMIC).
• Strong hands-on experience with physical verification tools (e.g., Siemens Calibre or IC Validator).
• Proficiency in scripting languages (Tcl, Python, or Perl) for workflow automation.
• Strong problem-solving skills and the ability to operate effectively in a multi-site R&D engineering environment.