Front-End Integration Engineer: RTL/Synthesis & UPF Expert

UST Malaysia; Bayan Lepas; Presencial; MYR 120.000 - 180.000; Jornada completa

Descripción de la vacante

UST Malaysia is seeking a Front End Integration Engineer to perform IP-level FEInt tasks. You will synthesize, lint, and verify IP blocks, addressing CDC/LEC and UPF concerns. Collaboration with verification, architecture, and backend teams is essential for a smooth IP handoff.

The ideal candidate has 3+ years in FEInt, strong SystemVerilog and scripting skills, and hands-on experience with VCS/Verdi/DVE in a modern ASIC/SoC flow.

Formación

• Bachelor's degree in Electrical/Computer Engineering or related field.
• At least 3 years of FEInt experience with IP blocks.
• Strong expertise in synthesis, linting, CDC, LEC and UPF.
• Proficient in RTL design and SystemVerilog; scripting with Perl/Python/TCL.
• Experience with VCS, Verdi, DVE; familiarity with AMBA/AXI/AHB.

Responsabilidades

• Conduct synthesis and optimization of IP blocks.
• Perform linting to ensure code quality and adherence to design guidelines.
• Conduct CDC analysis to identify clock domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis.
• Implement UPF methodologies for power-aware design and low-power verification.
• Collaborate with verification, architecture, and backend teams for IP integration.

Conocimientos

Synthesis

Linting

CDC

LEC

UPF

RTL design

SystemVerilog

VCS

Verdi

DVE

Debugging

Teamwork

Communication

Educación

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Herramientas

Perl

Python

TCL

VCS

Verdi

DVE

UVM

Descripción del empleo

UST Malaysia is seeking a Front End Integration Engineer to perform IP-level FEInt tasks. You will synthesize, lint, and verify IP blocks, addressing CDC/LEC and UPF concerns. Collaboration with verification, architecture, and backend teams is essential for a smooth IP handoff.

The ideal candidate has 3+ years in FEInt, strong SystemVerilog and scripting skills, and hands-on experience with VCS/Verdi/DVE in a modern ASIC/SoC flow.