ASIC Front-End Integration Engineer (RTL, Synthesis, CDC, LEC, UPF)

UST Malaysia; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST Malaysia is seeking a Front End Integration Engineer to perform IP-level FEInt tasks. You will synthesize, lint, and verify IP blocks, addressing CDC/LEC and UPF concerns. Collaboration with verification, architecture, and backend teams is essential for a smooth IP handoff.

The ideal candidate has 3+ years in FEInt, strong SystemVerilog and scripting skills, and hands-on experience with VCS/Verdi/DVE in a modern ASIC/SoC flow.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• At least 3 years of FEInt experience with IP blocks.
• Strong expertise in synthesis, linting, CDC, LEC and UPF.
• Proficient in RTL design and SystemVerilog; scripting with Perl/Python/TCL.
• Experience with VCS, Verdi, DVE; familiarity with AMBA/AXI/AHB.

Responsibilities

• Conduct synthesis and optimization of IP blocks.
• Perform linting to ensure code quality and adherence to design guidelines.
• Conduct CDC analysis to identify clock domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis.
• Implement UPF methodologies for power-aware design and low-power verification.
• Collaborate with verification, architecture, and backend teams for IP integration.

Skills

Synthesis

Linting

CDC

LEC

UPF

RTL design

SystemVerilog

VCS

Verdi

DVE

Debugging

Teamwork

Communication

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Tools

Perl

Python

TCL

VCS

Verdi

DVE

UVM

Job description

We are seeking a Front End Integration Engineer to perform IP-level FE Integration (FEInt) tasks. The ideal candidate will have expertise in synthesis, linting, CDC (Clock Domain Crossing), LEC (Logical Equivalence Checking), UPF (Unified Power Format), and related front-end implementation and verification methodologies. Exposure to Physical Design (PD) and Static Timing Analysis (STA) flows is highly desirable.
Responsibilities:Conduct synthesis and optimization of IP blocks.Perform linting to ensure code quality and adherence to design guidelines.Conduct CDC analysis to identify and address potential clock domain crossing issues.Perform LEC to ensure design consistency before and after synthesis.Implement UPF methodologies for power-aware design and low-power verification.Collaborate with verification, architecture, and backend teams to ensure seamless IP integration and handoff.
Qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.At least 3 years of experience in Front End Integration (FEInt) tasks.Strong expertise in synthesis, linting, CDC, LEC, and UPF methodologies.Proficient in industry-standard EDA tools.Rich verification experience (block-level or SoC-level); simulation and formal verification experience are additional advantages.Good understanding of RTL design and SystemVerilog. Proficiency in scripting languages such as Perl, Python, or TCL. UVM and verification experience are considered an advantage.Strong debugging capabilities with hands-on experience in VCS, Verdi, and DVE tools.Familiarity with standard AMBA/AXI/AHB interface protocols.Strong problem-solving, analytical, communication, and teamwork skills.
Preferred Qualifications:Knowledge of Physical Design (PD) flows, including floorplanning, place-and-route, power planning, and timing closure concepts.Experience with Static Timing Analysis (STA) and timing sign-off methodologies.Familiarity with front-end and back-end design handoff processes.Understanding of timing constraints development and timing/debug analysis.Experience working with advanced-node ASIC/SoC development flows is an advantage.