Digital Design & DoE Engineer for Test-Chip Yield

GLOBALFOUNDRIES SINGAPORE PTE. LTD.; Johor Bahru; On-site; MYR 50,000 - 80,000; Full time

Job summary

GlobalFoundries is seeking a Digital Design and Implementation Engineer to design and implement DoE blocks for standard cells and memory macros, assisting yield development and IP characterization. This role covers RTL development, synthesis, floorplanning, and timing analysis in a fast-paced semiconductor environment.

You will work with industry tools to drive the full digital implementation flow, perform DRC/LVS/DFM checks, and ensure design integrity through timing closure and logical

Qualifications

• Degree in Electrical / Electronic Engineering or a related field.
• Experience in digital physical design is preferred.
• Basic Verilog, Python or scripting knowledge.
• Familiarity with Synopsys or Cadence digital tools.

Responsibilities

• Develop DoE blocks for standard cells and memory macros to support yield measurements and characterization.
• Create and modify RTL, iterating parameters for optimal cell utilization within timing constraints.
• Drive the full digital implementation flow: synthesis, floorplan, power mesh, and place & route.
• Run physical verification (DRC, LVS, DFM, MAS) and resolve violations.
• Perform timing extraction and static timing analysis to close timing.
• Execute logical equivalence checks to ensure design integrity.

Skills

Digital design experience

RTL development

Timing analysis

Education

Electrical / Electronic Engineering degree

Tools

VCS

ICC2

Genus

Innovus

Virtuoso

Job description

GlobalFoundries is seeking a Digital Design and Implementation Engineer to design and implement DoE blocks for standard cells and memory macros, assisting yield development and IP characterization. This role covers RTL development, synthesis, floorplanning, and timing analysis in a fast-paced semiconductor environment.

You will work with industry tools to drive the full digital implementation flow, perform DRC/LVS/DFM checks, and ensure design integrity through timing closure and logical