DFT/DFX Verification Engineer – SoC Debug & Test

Thundersoft; George Town; On-site; MYR 100,000 - 145,000; Full time

Job summary

Thundersoft is seeking a DFT/ DFx Verification Engineer to verify architecture, design, and implementation of critical DFT and DFD features. You will work with global design teams on test development, tool integration, and ongoing process improvements.

The role emphasizes robust debugging, automation, and collaboration across RTL, firmware, and test environments. The ideal candidate has 3–5 years in DFT verification, strong SystemVerilog/UVM experience, and hands-on scripting skills.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field.
• 3–5 years of DFT Design Verification with strong debugging abilities.
• Experience with SystemVerilog/UVM testbenches for SoCs, including GLS & SDF verifications.
• Hands-on with DFT/DFX methods: Scan, ATPG, MBIST, Boundary Scan, or equivalents.
• Advanced scripting for automation and testbench infra (Tcl, Python, Perl).
• Strong knowledge of digital RTL design and verification flows.

Responsibilities

• Collaborate with architects and firmware engineers to verify new DFT features.
• Estimate effort to write feature tests and adjust test environment.
• Build directed and random DFT verification tests.
• Debug test failures; coordinate with RTL/DFT to fix defects.
• Enhance legacy DFT test plans for new feature development.
• Reproduce post-silicon issues in pre-silicon environment.
• Conduct silicon debug and root-cause analysis with minimal logs.
• Use JTAG protocols for debugging and validation.

Skills

DFT/DFX verification

SystemVerilog/UVM

Debug without logs

Scripting (Tcl, Python, Perl)

RTL design & verification

CG/BA or debugging methodologies

Education

Bachelor's or Master's in Electrical/Electronics/Computer Engineering

Tools

Simulation tools

Emulation tools

GLS & SDF verification

Job description

Thundersoft is seeking a DFT/ DFx Verification Engineer to verify architecture, design, and implementation of critical DFT and DFD features. You will work with global design teams on test development, tool integration, and ongoing process improvements.

The role emphasizes robust debugging, automation, and collaboration across RTL, firmware, and test environments. The ideal candidate has 3–5 years in DFT verification, strong SystemVerilog/UVM experience, and hands-on scripting skills.