SoC DFT Engineer — AI-Driven Test & Debug

Intel Corporation; Penang; Hybrid; MYR 180,000 - 240,000; Full time

Job summary

Intel Corporation in Malaysia (Penang) is seeking a DFT Design Engineer to shape testability, debuggability and reliability of complex SoC designs. You will work with cross-functional teams to develop DFT/DFD methodologies, optimize workflows with AI, and enhance post-silicon efficiency.

Bring 5+ years in DFT/SoC design, RTL experience (Verilog/VHDL/SystemVerilog), and familiarity with DFT tools such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Modus.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in DFT, SoC design, or related semiconductor design areas.
• Expertise in RTL design using Verilog, VHDL, or SystemVerilog.

Responsibilities

• Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency.
• Collaborate with design, verification, and manufacturing teams to define and optimize post silicon strategies and requirements.
• Integrate DFT/DFD features into RTL and ensure verification of design for testability requirements.
• Collaborate with post-silicon teams to debug and validate DFT features.
• Stay current with emerging trends, AI adoption and technologies in DFT/DFD to ensure best practices are incorporated into workflows.

Skills

RTL languages

DFT/SoC design

AI in DFT workflows

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

Mentor Tessent

Cadence Modus

Python scripting

Job description

Intel Corporation in Malaysia (Penang) is seeking a DFT Design Engineer to shape testability, debuggability and reliability of complex SoC designs. You will work with cross-functional teams to develop DFT/DFD methodologies, optimize workflows with AI, and enhance post-silicon efficiency.

Bring 5+ years in DFT/SoC design, RTL experience (Verilog/VHDL/SystemVerilog), and familiarity with DFT tools such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Modus.