Design Verification Manager

UST Malaysia; George Town; On-site; MYR 180,000 - 300,000; Full time

Job summary

UST in Malaysia is seeking a senior verification leader with 10+ years of experience to guide the verification team on strategy, test plans, and execution for ASIC/SoC projects. You will participate in technical assessments, drive improvements and best practices across the team, and support project planning and milestone tracking in collaboration with the project manager.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or related field.
• 10+ years of ASIC/SoC verification experience using SystemVerilog and UVM.
• Strong understanding of digital design and verification fundamentals.
• Experience in leading a team.

Responsibilities

• Provide technical guidance to the verification team on strategy, test plans, and execution.
• Participate in and contribute to technical assessments, reviews, and issue resolutions.
• Drive technical improvements and best practices across the team.
• Support project planning, resource allocation, performance management and milestone tracking in collaboration with the project manager and/or lead.

Skills

Leadership

ASIC/SoC verification experience

Digital design fundamentals

Test planning & execution

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering or related field

Tools

SystemVerilog

UVM

Job description

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact‑touching billions of lives in the process. Visit us at www.UST.com

Experience: 10+ years

Job Description

• Provide technical guidance to the verification team on strategy, test plans, and execution.
• Participate in and contribute to technical assessments, reviews, and issue resolutions.
• Drive technical improvements and best practices across the team
• Support project planning, resource allocation, performance management and milestone tracking in collaboration with the project manager and/or lead
• At least 10 years of relevant experience

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC/SoC verification using SystemVerilog and UVM.
• Strong understanding of digital design and verification fundamentals.
• Experience with managing team

Contact

Ms. Anna - WhatsApp: [phone]