Senior AMS Verification Architect

UST; Seberang Perai; On-site; MYR 140,000 - 210,000; Full time

Job summary

UST in Penang, Malaysia, seeks a Senior Analog Mixed-Signal (AMS) Verification Engineer to lead verification strategies for complex analog and mixed-signal ICs, collaborating with analog/digital design, architecture, test and validation teams from specification through silicon validation.

The role requires 7+ years of AMS verification experience, hands-on proficiency with Cadence Spectre, AMS Designer, Xcelium and Siemens Symphony, and strong SystemVerilog/Verilog RTL skills; you will develop

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Microelectronics, or related discipline.
• 7+ years of analog/mixed-signal IC verification, design, modeling, or simulation experience.
• Hands-on experience in AMS verification and simulation.
• Experience with Cadence Spectre, AMS Designer, Xcelium, Siemens Symphony, or similar.
• Strong understanding of analog/mixed-signal circuits and system-level interactions.
• Knowledge of SystemVerilog and Verilog RTL.
• Experience developing verification plans, test cases, simulation environments, and automated regressions.

Responsibilities

• Define AMS/System verification strategies, plans, test cases, and coverage.
• Develop mixed-signal testbenches, checkers, behavioral models, and automated regression flows.
• Perform transistor-level, behavioral, and mixed-abstraction simulations using AMS simulation tools.
• Verify analog and mixed-signal functions including LDOs/regulators, DC/DC converters, references, oscillators, amplifiers, charge pumps, protection circuits, and power sequencing.
• Verify analog/digital interactions, including register-controlled functions, state machines, fault handling, startup/shutdown, and test modes.
• Develop reusable verification environments using SystemVerilog/UVM where applicable.
• Debug complex AMS simulation failures and collaborate with design teams on root-cause analysis.
• Track verification progress and participate in design/specification reviews.
• Support silicon bring-up, validation, and simulation-to-silicon correlation when required.
• Drive verification methodology improvements and mentor junior engineers.

Skills

AMS verification

SystemVerilog

Verilog RTL

Debugging

Problem-solving

Education

Bachelor's or Master's degree in Electrical/Electronics Engineering, Microelectronics

Tools

Cadence Spectre

AMS Designer

Xcelium

Siemens Symphony

Python

Tcl

Perl

Shell scripting

Job description

UST in Penang, Malaysia, seeks a Senior Analog Mixed-Signal (AMS) Verification Engineer to lead verification strategies for complex analog and mixed-signal ICs, collaborating with analog/digital design, architecture, test and validation teams from specification through silicon validation.

The role requires 7+ years of AMS verification experience, hands-on proficiency with Cadence Spectre, AMS Designer, Xcelium and Siemens Symphony, and strong SystemVerilog/Verilog RTL skills; you will develop