FPGA IP Software Development Engineer

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 60,000 - 90,000; Full time

Job summary

Altera Semiconductor Technology (M) Sdn. Bhd. is seeking an electronics engineer to perform RTL design and simulation for IPs and subsystems in the FPGA domain, contributing to the development flow and verification. You will analyze issues and present robust solutions throughout the design cycle.

The role emphasizes hands-on experience with FPGA tools (Xilinx/Intel), HDL languages, and a collaborative approach with verification teams to deliver reliable digital designs.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Hands-on RTL design, FPGA prototyping, or digital system design through internships or academic projects.
• Experience with FPGA tools and flows using Xilinx or Intel FPGA ecosystems.
• Ability to debug design issues and document technical topics clearly.

Responsibilities

• Perform RTL design coding and simulation to develop IPs and subsystems.
• Understand FPGA development flow and contribute to verification plans.
• Analyze problems and present practical solutions.

Skills

RTL design & HDL

FSMs & pipelines

Simulation & verification

SystemVerilog assertions (SVA)

UVM awareness

Synthesis & timing analysis

AMBA protocols

Industry standards (PCIe/USB/DDR/MIPI)

Education

Bachelor’s or Master’s in EE/CE

Tools

ModelSim

VCS

Xcelium

Vivado

Quartus

Job description

Job Details: Job Description: Join the exciting new journey of Altera as we march towards a stand‑alone company. From the IoT to the data center, Altera offers a broad portfolio of programmable logic solutions that allow customers to solve a wide variety of system level challenges.

Responsibilities

• Perform logic design RTL coding and simulation to develop IPs and subsystem designs.
• Understand processes in the FPGA development flow.
• Analyze the problem at hand and present solutions.

Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Technical Skills:
  • RTL Design & Hardware Description Languages: Basic experience with Verilog or VHDL.
  • Combinational & sequential logic, finite state machines (FSMs), and pipeline architectures.
  • Simulation & Verification: Exposure to testbenches, functional simulation using ModelSim, VCS, or Xcelium.
  • Basic understanding of SystemVerilog assertions (SVA) and testbenches; awareness of UVM is a plus.
  • Synthesis & Timing Analysis (Preferred): Basic knowledge of synthesis flow (Design Compiler, Genus, or Vivado). Understanding of setup/hold timing violations and static timing analysis.
  • Scripting & Automation: Basic understanding of AMBA protocols (AXI, AHB, APB); awareness of memory subsystems, clock domains, and reset strategies.
  • Exposure to industry standards like PCIe, USB, DDR, or MIPI is a plus.
• Experience & Projects: Internships or academic projects related to RTL design, FPGA prototyping, or digital system design. Hands‑on experience in FPGA‑based projects using Xilinx or Intel FPGA tools is an advantage.
• Soft Skills:
  • Problem‑solving: Ability to debug design issues.
  • Communication: Ability to document designs and discuss technical topics clearly.
  • Collaboration: Willingness to work with verification and backend teams.

Job Type

Regular

Shift

Shift 1 (Malaysia)

Location

Penang 15, Penang, Malaysia

Equal Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.