ASIC/FPGA Design Engineer

Intel Corporation; Penang; On-site; MYR 80,000 - 120,000; Full time

Job summary

A leading semiconductor company in Malaysia seeks an experienced ASIC/FPGA Design Engineer to develop and maintain RTL designs using Verilog/System Verilog. Candidates should have 5+ years in RTL/Logic design, strong analytical and problem-solving skills, and the ability to collaborate effectively with cross-functional teams. Knowledge of guidelines and coding standards is essential, alongside familiarity with tools like Quartus and Vivado. The role offers a hybrid work model, balancing on-site and off-site work.

Qualifications

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog.
• Experience with Packet Based Protocols such as PCIe, USB, SPI, and I2C.
• Familiarity with internal and third-party logic design tools.

Responsibilities

• Develop and maintain RTL designs using Verilog/System Verilog.
• Perform functional simulation and verification.
• Collaborate closely with architects and verification engineers.

Skills

RTL/Logic design

Verilog/System Verilog

Analytical ability

Problem solving

Communication skills

Teamwork

Tools

Quartus

Vivado

Logic analyzers

Protocol analyzers

Job description

# **Welcome!**## .ASIC/FPGA Design Engineer page is loaded## ASIC/FPGA Design Engineerlocations: Malaysia, Penangtime type: Full timeposted on: Posted Todayjob requisition id: JR0280623# **Job Details:**## Job Description:* Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications.* Debug and resolve design and simulation issues, collaborate closely with architects, verification engineers, and system teams to clarify requirements, and support design integration, bring-up, and issue resolution.* Ensure high design quality by following coding standards and maintaining proper technical documentation.## **Qualifications:**Minimum qualifications are required to be initially considered for this position.Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:* 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog RTL coding.Preferred Qualifications:* Experience with Packet Based Protocols such as PCIe, USB, SPI, I2C and etc is an advantage.* Experience in agentic AI is an advantage.* Demonstrable experience in logic design and writing RTL in Verilog or System Verilog.* Familiarity with a range of internal and 3rd-party logic design tools.* Strong analytical ability, problem solving and communication skills.* Gate-level understanding of RTL and synthesis - i.e. understand how RTL looks like/behaves after it is synthesized into gates.* Experience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issues.* Strong communication and teamwork still.* Ability to work independently and at various levels of abstraction.* Ability to lead a team of designer.* Knowledge in FPGA design and debug with FPGA tools like Quartus/Vivado will be an added advantage.* Knowledge on embedded SW which using NIOS or ARM processor is an added advantage.* Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.## Job Type:Experienced Hire## Shift:Shift 1 (Malaysia)## Primary Location:Malaysia, Penang## Additional Locations:## Business group:Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change.\*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.