Application Engineer -Timing and EM/IR Signoff

Cadence; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Cadence in Malaysia is seeking a Lead Application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region.

You will combine hands-on physical design expertise with technical leadership and customer engagement to help customers achieve optimal performance, power and area (PPA) on advanced technology nodes, while collaborating with RTL design teams to ensure successful tapeout.

Qualifications

• BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
• Experienced with ASIC design flow, static timing analysis, EM/IR analysis.
• Prior knowledge on Timing and IR drop closure in 3DIC technologies would be an added advantage.
• Able to assume responsibility for a variety of technical tasks and to work independently.
• Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own design.
• Self-motivated, able to work as a team player, and good English communication skills.

Responsibilities

• The timing closure, power/signal integrity signoff and EM/IR signoff will be performed by the candidate.
• The candidate will have the opportunity to work on many varieties of challenging designs, e.g. low power and high speed designs at the latest technology node.
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
• The candidate will work closely with RTL design team to ensure successful tapeout.

Skills

Physical design

Static timing analysis

EM/IR signoff

Team leadership

English communication

Education

BS/MS in EE/CS

Job description

Lead application Engineer – Timing and EM/IR Signoff

Location: Malaysia

Job Overvie

wWe are seeking a Lead application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region

.In this role, you will combine deep hands-on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption

• The candidate will perform the iming closure, power/signal integrity signoff and EM/IR signo
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology node
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow developmen
• The candidate will work closely with RTL design team to ensure successful tapeout

Requiremen

• BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verificatio
• Experienced with ASIC design flow, static timing analysis, EM/ IR anlys
• Prior knowledge on Timing and IR drop closure in 3DIC technologies would be an added advanra
• Able to assume responsibility for a variety of technical tasks and to work independent
• Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own desig
• Self-motivated, able to work as a team player, and good English communication skil ls